Browse Prior Art Database

Peripheral Component Interconnect Bus Target Timeout Counter

IP.com Disclosure Number: IPCOM000114675D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Curry, SE: AUTHOR [+2]

Abstract

Disclosed is a means to terminate Peripheral Component Interconnect (PCI) bus cycles which have been claimed by target devices, but never target terminated. Desktop PowerPC* systems use a timer in the form of a bus clock counter to resolve this problem.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 70% of the total text.

Peripheral Component Interconnect Bus Target Timeout Counter

      Disclosed is a means to terminate Peripheral Component
Interconnect (PCI) bus cycles which have been claimed by target
devices, but never target terminated.  Desktop PowerPC* systems use a
timer in the form of a bus clock counter to resolve this problem.

      Version 2.0 of the PCI bus specification provides no means of
terminating a bus cycle which has been claimed by a target device,
but never target terminated.  A broken or incorrectly programmed
device or adapter may then cause the bus and system to hang.  A
mechanism is needed to avoid this condition.

      The PCI specification does call for the use of an internal
Latency Timer (LT) in each PCI bus master.  This timer controls the
time a bus master may remain master once its GNT# signal has been
de-asserted.  However, the operation of this timer is to control the
length of a burst operation, and is reset based on the PCI FRAME#
signal.  In a single-beat transfer, FRAME# may only be asserted for a
single cycle, and this problem would still exist.

      This problem can be solved by implementing a timer in the form
of a bus clock counter.  The counter is reset for each bus
transaction when claimed by a target device or adapter (assertion of
PCI bus signal DEVSEL#).

By PCI bus protocol, the target must terminate a cycle by either:
  o  asserting TRDY# to signal successful transfer of data
  o  asserting STOP# (and/or TRDY#)...