Browse Prior Art Database

Power-On Self-Test and Diagnostics Functions for Sixteen Bit Wide Small Computer System Interface Personal Computers

IP.com Disclosure Number: IPCOM000114677D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 4 page(s) / 133K

Publishing Venue

IBM

Related People

Cook, DC: AUTHOR [+4]

Abstract

Described is an architectural implementation to provide Power-On Self Test (POST) capabilities so as to fully test the Small Computer System Interface (SCSI) bus and the SCSI type functions, as used on Personal Computers (PC's). The implementation is designed for PCs which utilize a SCSI chip in a Micro Channel* (MC) adapter with a sixteen bit wide data bus and connections with up to fifteen SCSI devices.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 49% of the total text.

Power-On Self-Test and Diagnostics Functions for Sixteen Bit Wide
Small Computer System Interface Personal Computers

      Described is an architectural implementation to provide
Power-On Self Test (POST) capabilities so as to fully test the Small
Computer System Interface (SCSI) bus and the SCSI type functions, as
used on Personal Computers (PC's).  The implementation is designed
for PCs which utilize a SCSI chip in a Micro Channel* (MC) adapter
with a sixteen bit wide data bus and connections with up to fifteen
SCSI devices.

      The POST and diagnostic functions enable a sixteen bit SCSI
device to arbitrate, select or re-select itself, and to conduct
information and asynchronous data transfers.  In normal operation, a
SCSI chip has the ability to act as both a target and an initiator.
In test/diagnostic mode, a set of registers on the SCSI chip will
complete the nexus with the functional hardware.  Test mode register,
h'40'; First-In-First-Out (FIFO) test data register, h'42'; SCSI
signal test register, (h'44'); SCSI data test register, h'46'; and
SCSI parity register, h'48', are controlled by the microprocessor in
order to emulate the other devices in the nexus.

The following eighteen items illustrate a typical use of the test
registers:
  1.  The functional logic in the chip has been programmed to
       arbitrate, select its own identification (ID), send a message
       byte, and send a command byte.
  2.  The functional logic arbitrates and wins.
  3.  The functional logic selects itself by driving BSY, SEL, ATN
and
       its own ID, and then releasing BSY.
  4.  The microprocessor monitors BSY, SEL, ATN and its own ID.  The
       microprocessor detects BSY going inactive.
  5.  The microprocessor responds to the selection by setting the
test
       mode enable bit in the test mode register, h'40', and the SCSI
       BSY bit in the SCSI signal test register, h'44'.
  6.  The functional logic drops SEL to complete the selection
process.
  7.  The microprocessor changes to message out phase by resetting
the
       input/output (I/O) and setting C/D and MSG in the SCSI signal
       test register.
  8.  The microprocessor sets the REQ bit in the signal test register
       and monitors for acknowledgement (ACK) to go active.
  9.  The functional logic drives the message byte onto the SCSI bus
       and then asserts the ACK.
 10.  The microprocessor detects ACK.
 11.  The microprocessor reads the SCSI data test register, h'46',
and
       the SCSI parity register, h'48', to determine the values of
data
       and parity on the SCSI bus.  It then de-asserts REQ and
monitors
       ACK.
 12.  The functional logic de-asserts ACK and waits for the phase
       change.
 13.  The microprocessor detects the ACK being active.  It changes
the
       phase to command out by resetting the MSG bit in the SCSI
signal...