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Browse Prior Art Database

Sampling of a Synchronously Transmitted Data Stream

IP.com Disclosure Number: IPCOM000114696D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 4 page(s) / 160K

Publishing Venue

IBM

Related People

Kern, R: AUTHOR [+2]

Abstract

The sampling of serially transmitted data signals may take place at a frequency which is significantly higher than the transmission frequency. The device described herein avoids such higher sampling frequency by generating time shifted images of the data signals received which than are sampled simultaneously with the latter. The parallel sampling of the input data and its images in a certain time interval has the same effect as a multiple sampling in the same time interval.

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This is the abbreviated version, containing approximately 40% of the total text.

Sampling of a Synchronously Transmitted Data Stream

      The sampling of serially transmitted data signals may take
place at a frequency which is significantly higher than the
transmission frequency.  The device described herein avoids such
higher sampling frequency by generating time shifted images of the
data signals received which than are sampled simultaneously with the
latter.  The parallel sampling of the input data and its images in a
certain time interval has the same effect as a multiple sampling in
the same time interval.

      Fig. 1 shows a general circuit diagram of a sampling device
using this method.  The digital data signal received on line 1 is
stored in latch L1 and in parallel submitted to a variable delay line
2 the elements V1, V2, ...Vn-1 of which are set and dynamically reset
by a digital phase locked loop 3.  Each of the delay elements V1, V2,
...Vn-1 is connected to one of latches L2, L3, ...Ln-1 which are
arranged in parallel to latch L1.  These latches are connected to an
OR circuit 4.  Sampling takes place for all latches in parallel and
the
sampled data signal is received at the output 5 of the OR circuit 4.

      This device may be used to sample serial data streams the
transmission rate of which corresponds to the sampling frequency or
is even an integer multiple of the latter.  The device may also be
used to recognize parallel data asynchronously transmitted which are
only valid during a single sample interval.

      Fig. 2 shows a circuit for synchronization and deserialization
of an asynchronous data stream of 20 MBit/sec by using a system
timing frequency of 20 MHz which corresponds to a timing interval of
50 nsec.  The protocol of the serial signal provides for a start bit
followed by eight data bits and a stop bit where the start bit is
represented by a "1" and the stop bit is represented by a "0".  The
circuit shown permits to recognize the position of the first positive
transition of the input signal, i.e., the begin of the start bit, in
relationship to the system timing to achieve a sampling close to the
middle of the bit intervals.  For this purpose, the input signal from
line 11 is led to L1-latch 12 without delay, via V1-delay circuit 16
to L2-latch 13 with a delay of about 17 nsec, which is 1/3 of 50
nsec, and via V2-delay circuit 17 to L3-latch 14 with a delay of
about 33 nsec, which is 2/3 of 50 nsec.  The delay circuits 16 and 17
are controlled by a digital phase locked loop circuit 18 to adjust
the delays according to variations of the signal transmission
frequency.

      The input signal S1 from line 11 is led to L1-latch 12 through
an AND circuit 21 and an OR circuit 22.  AND circuit 21 is
conditioned by an inverted output signal of an OR circuit 23 which is
present as long none of the latches 12 to 14 is in the set status.
The
set status of L1-Latch 12 is maintained via a feedback of its set
status output Q1 and OR circuit 22.  Accordingly, the output si...