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Controlled Impedance Very Large Scale Integration Interconnects with On-Chip Decoupling Capacitors

IP.com Disclosure Number: IPCOM000114699D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 4 page(s) / 104K

Publishing Venue

IBM

Related People

Dinger, TR: AUTHOR [+3]

Abstract

A Very Large Scale Integration (VLSI) chip or packaging interconnect structure and fabrication methodology are disclosed which solves a number of electrical parasitic problems in high-performance systems. The structure allows control of the characteristic impedance of interconnects and dramatically reduces stray inductance, capacitive and inductive crosstalk, and additionally provides exceedingly large on-chip decoupling capacitance in the unused wiring track area of a given wiring level.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Controlled Impedance Very Large Scale Integration Interconnects with
On-Chip Decoupling Capacitors

      A Very Large Scale Integration (VLSI) chip or packaging
interconnect structure and fabrication methodology are disclosed
which solves a number of electrical parasitic problems in
high-performance systems.  The structure allows control of the
characteristic impedance of interconnects and dramatically reduces
stray inductance, capacitive and inductive crosstalk, and
additionally provides exceedingly large on-chip decoupling
capacitance
in the unused wiring track area of a given wiring level.

      The structure and method thereof are depicted in
Fig. 1.  Patterned metal signal lines are encased in a comformal
dielectric, such as CVD oxide or spin-on polymer.  The thickness of
this
layer is approximately equal to the line thickness and no more, so
gaps
between the lines are formed.  A metal-dielectric-metal stack such as
Ta/Ta(2)O(5)/Ta is then deposited.  The sample is then chem-mech
polished to leave the structure shown.  The result is narrow metal
"nailhead"-shaped lines between the interconnects, and large planar
capacitors in field areas where interconnects had not
existed.  Subsequent processing can be used to make contact to one or
both of the capacitor plates, as shown.

      The "nailhead" reference lines have a dramatic effect on
crosstalk and inductance, and supporting calculations are shown in
Fig. 2.  Here the total (C(11), L(11)) and crosstalk (C(12), L(12))
capacitances and inductances were calculated for four scenarios:
  1.  M2 line with ground planes/current returns on M1 and M3;
  2.  Same with M3 plane removed;
  3.  M1 and M3 removed, ground plane/current return in Si substrate;
  4.  Same with other M2...