Browse Prior Art Database

Instruction Cache for a Microcontroller

IP.com Disclosure Number: IPCOM000114701D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 4 page(s) / 232K

Publishing Venue

IBM

Related People

Bubb, CE: AUTHOR [+5]

Abstract

Disclosed is an apparatus and method for locally caching instructions used by a microcontroller. A hardware mechanism is used to detect if the instruction to be executed is in the cache. If the instruction is not in the cache, an interrupt is generated allowing the microcontroller to fetch the instruction from storage external to the microcontroller. The program that fetches the instructions determines where in the cache the fetched instructions should be placed and hence which instructions should be deleted.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 25% of the total text.

Instruction Cache for a Microcontroller

      Disclosed is an apparatus and method for locally caching
instructions used by a microcontroller.  A hardware mechanism is used
to detect if the instruction to be executed is in the cache.   If the
instruction is not in the cache, an interrupt is generated allowing
the microcontroller to fetch the instruction from storage external to
the microcontroller.  The program that fetches the instructions
determines where in the cache the fetched instructions should be
placed and hence which instructions should be deleted.

      The microcontroller described in this disclosure is part of a
larger computer system, and the instructions executed in this
microcontroller are stored in the system's main storage.  The
microcontroller has a small instruction cache that is not large
enough to hold all of the instructions for all of the programs that
it must execute.  The microcontroller fetches blocks of instructions
called segments from main storage as required.  The segments are not
strictly limited to instructions and can also consist of static data
such as branch tables.  Hardware facilities are provided to keep
track of the state of the cache and a microprogram executed by the
microcontroller fetches the segments.

      The microcontroller has a single 512 kilobyte address space
('00000'x through '7FFFF'x).  The first 32 K addresses ('00000'x
through '07FFF'x) are never fetched from main store and do not
contain instructions.  Addresses '00000'x through '01FFF'x access an
8 kilobyte scratch pad store called Local Working Store (LWS) which
is physically part of the microcontroller and addresses '02000'x
through '07FFF'x access memory mapped facilities consisting of
control registers and buffers that are used by the microcontroller to
perform its functions.  The address range from 32 K to 512 K
('08000'x through '7FFFF'x) can be fetched from main store and is
used for instructions and related data such as branch tables.

      The instruction cache is called Writeable Control Store (WCS)
and holds 8192 instructions; each instruction has four bytes.  An
image of the entire instruction address space is in main store and
this space is divided into 240 segments; each segment is 2048 bytes
(512 instructions).  WCS is divided into 16 segments and each of
these segments is also 2048 bytes.

      Two mapping tables (the segment table and the reverse lookup
table) in LWS keep track of which of the 240 segments of the
instruction address space are currently in the 16 WCS segments and
where these segments are in WCS.  In the segment table, there is one
LWS entry for each of the 240 segments.  To simplify addressing, the
LWS table has an additional unused 16 entries at the beginning,
making 256 entries (a power of 2).  Each table entry defines the
status of the corresponding segment in the instruction address space.
For example, the 18th entry (recall that the first 16 entries are
unus...