Browse Prior Art Database

Wafer Warpage Reduction Method for Silicon-on-Sapphire Wafer Processing

IP.com Disclosure Number: IPCOM000114708D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Gut, GM: AUTHOR [+5]

Abstract

Thermal expansion mismatch between sapphire and process deposited thin films in Silicon-on-Sapphire (SOS) technology results in excessive warpage of the substrate. This is especially true for large diameter substrates. Described is a method which solves the warpage problem by incorporating a technique which cuts through the deposited films at the edges of the chips. This separates the thin films into a large number of small regions thus relieving the stress and reducing warpage.

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Wafer Warpage Reduction Method for Silicon-on-Sapphire Wafer Processing

      Thermal expansion mismatch between sapphire and process
deposited thin films in Silicon-on-Sapphire (SOS) technology results
in excessive warpage of the substrate.  This is especially true for
large diameter substrates.  Described is a method which solves the
warpage problem by incorporating a technique which cuts through the
deposited films at the edges of the chips.  This separates the thin
films into a large number of small regions thus relieving the stress
and reducing warpage.

      Large diameter sapphire substrates present a manufacturability
problem to automated processing tools after the required thin films
are reposited on the substrate.  This is due to the very large
thermal expansion mismatch between the substrate and the thin films.

      This invention seeks to eliminate most of this warpage by
incorporating a process step which cuts through the deposited films
at certain points in the process when the induced strain starts to be
a problem.  These cuts are performed at the edges of the chips where
dicing normally occurs.  The cuts are executed using the normal
semiconductor processing tools which are used to manufacture the
chips.  The cutting process is combined with normal processing steps
thus no additional masking or processing is required.

      The wafer is modified from one continuous film with a given
area to a large number of small chips with the sa...