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Differential High-Speed Analog to Digital Converter

IP.com Disclosure Number: IPCOM000114715D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 4 page(s) / 121K

Publishing Venue

IBM

Related People

Goetschel, CJ: AUTHOR [+8]

Abstract

A differential Analog to Digital Converter (ADC) design is disclosed where the signal to be digitized is passed through a differential resistor ladder. A unique assignment of comparators to the differential resistor ladder taps combined with low impedance drive on both ends of the ladder drops the worst case ladder impedance seen by any comparator by a factor of eight. The eight times lower impedance increases the bandwidth of the ADC.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 41% of the total text.

Differential High-Speed Analog to Digital Converter

      A differential Analog to Digital Converter (ADC) design is
disclosed where the signal to be digitized is passed through a
differential resistor ladder.  A unique assignment of comparators to
the differential resistor ladder taps combined with low impedance
drive on both ends of the ladder drops the worst case ladder
impedance seen by any comparator by a factor of eight.  The eight
times lower impedance increases the bandwidth of the ADC.

      A single-ended flash converter uses a series string of 2**n
resistors (for a n bit converter) to divide down a reference voltage
range.  A series string of (2**n)-1 comparators have their minus
inputs hooked to each of the (2**n)-1 center taps between resistors.
All of the comparator Plus inputs hook together to form the input.
The series resistors pass no signal and merely divide down the full
scale input reference voltage into Most Significant Bits (MSBs) to
compare the signal.

      To convert this topology to differential, it is required to
have resistor ladders hooked to both the minus and plus inputs of the
comparators and pass signal through them.  Prior designs have used
2**n resistors on each of the differential signal polarities.  This
results in 2**(n+1) resistors for an n bit converter.  Prior designs
have also only provided low impedance to one end of each resistor
ladder while the other end is driven by a high impedance (collector
or drain).  The design in this disclosure does not increase the
number of resistors from a single-ended design, namely 2**n, and
achieves low impedance on both ends of each resistor ladder, while
driving differentially both ends of the ladder.
   CMP+  CMP-  CODE  TCODE        CMP+  CMP-  CODE TCODE
   P0    N32   -32   *NOT USED*  P17   N16     1   31
   P1    N32   -31   63 BOTTOM   P17   N15     2   30
   P1    N31   -30   62          P18   N15     3   29
   P2    N31   -29   61          P18   N14     4   28
   P2    N30   -28   60          P19   N14     5   27
   P3    N30   -27   59          P19   N13     6   26
   P3    N29   -26   58          P20   N13     7   25
   P4    N29   -25   57          P20   N12     8   24
   P4    N28   -24   56          P21   N12     9   23
   P5    N28   -23   55          P21   N11    10   22
   P5    N27   -22   54          P22   N11    11   21
   P6    N27   -21   53          P22   N10    12   20
   P6    N26   -20   52          P23   N10    13   19
   P7    N26   -19   51          P23   N9     14   18
   P7    N25   -18   50          P24   N9     15   17
   P8   ...