Browse Prior Art Database

Capacitance Target-Driven Cell Placement

IP.com Disclosure Number: IPCOM000114727D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 4 page(s) / 206K

Publishing Venue

IBM

Related People

Haeussier, DA: AUTHOR

Abstract

Described is a function used during physical design that attempts to minimize the number of nets that exceed the capacitance targets used during logic design before wiring routing is performed. The function identifies after cell placement the nets that exceeded their capacitance targets and generates weightings for nets to force the nets to meet their targets during a second iteration of placement.

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Capacitance Target-Driven Cell Placement

      Described is a function used during physical design that
attempts to minimize the number of nets that exceed the capacitance
targets used during logic design before wiring routing is performed.
The
function identifies after cell placement the nets that exceeded
their capacitance targets and generates weightings for nets to force
the nets to meet their targets during a second iteration of
placement.

      A common problem near the end of the chip design cycle is that
the physical designer has created a design with wires that do not
meet the capacitance targets used by the logic designer during
simulation.  An even bigger problem occurs when some of the nets
created during physical design have a greater capacitance than the
maximum allowable for the driver of a net.  When physical design is
complete and the logic designer simulates the wired design, a number
of nets will be found not to meet their pre-physical design net
capacitance targets or nets will be found to have total capacitances
that are greater than the maximum driving capability of the driver
pin in a net.   The nets that are over their capacitance targets than
need to be reworked.  Reworking a net can be accomplished by
inserting into the logic a device that has the ability to drive a
greater capacitance load or it can be done by the logic designer
asking the physical designer to re-wire in another configuration the
nets that have capacitance problems.  Either one of these methods
causes a design iteration and increases the overall time spent in the
design cycle.  The changes caused by each iteration can also cause
additional nets to not make their capacitance targets, possibly
requiring further iterations.  If the physical designer can do a
placement which has a high probability that the nets in the design
will make their pre-physical design targets, the potential for
multiple iterations between physical and logical design to fix
capacitance problems will be eliminated and the overall design time
will be reduced.  This disclosure documents a function which a chip
physical designer can use to increase the probability that all nets
on a chip will make their targets after detailed wiring of the
design.  The function described will also the physical designer to
identify the nets that have a lower probability of making their
capacitance targets before wiring a design.  The nets that do not
make their capacitance targets include both the nets that had
estimated wiring capacitance greater than the logic simulated
capacitance targets and the nets that have too large of an overall
capacitance for the driver pin of the net to be able to drive.  A
logic designer will normally insure that a design meets its estimated
capacitance targets before the design goes to physical design.  If
physical designer can wire the design to meet or beat the estimated
maximum capacitances set by the logic designer, the wired design
should be...