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Browse Prior Art Database

Microcontroller Control Store Fault Tolerance

IP.com Disclosure Number: IPCOM000114728D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 4 page(s) / 120K

Publishing Venue

IBM

Related People

Bubb, CE: AUTHOR [+2]

Abstract

Errors caused by single bit stuck faults in the control store array of a microcontroller are avoided by altering the polarity of the instruction stored in the location with the stuck bit. Each time the array is written, it is immediately read to determine if the instruction is correct. If it is not, the instruction is complemented and written into the array. Included in the array with the instruction is a bit that specifies that the data is complemented.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Microcontroller Control Store Fault Tolerance

      Errors caused by single bit stuck faults in the control store
array of a microcontroller are avoided by altering the polarity of
the instruction stored in the location with the stuck bit.  Each time
the array is written, it is immediately read to determine if the
instruction is correct.  If it is not, the instruction is
complemented and written into the array.  Included in the array with
the instruction is a bit that specifies that the data is
complemented.

      The traditional method of providing array fault tolerance is to
use ECC.  This approach requires many circuits and slows down both
the read and write access to the array.  The ECC approach also covers
transient errors in the array (the contents changed from the time it
was written to the time it is read).

      The control store of a microcontroller that is part of a larger
computer system has specific properties that allow a fault tolerant
approach that requires much less hardware than using ECC.  First,
since
a copy of the instructions always resides in main store, transient
errors can be corrected by refetching the instruction.  Second,
a control store can be written relatively slowly so there is
sufficient time to read the contents for verification.  Third, the
read access must be kept to a minimum to improve the performance of
the branch instructions without adding complicated branch guess
and/or
branch history logic.  Because of these properties, only permanent
faults (such as stuck bits) require a hardware solution.  The
fault tolerant design described in this disclosure corrects at
least one stuck bit fault per instruction.  The design assumes that
the faults are 'stuck' in that the faulty bit is always on or always
off.  The polarity of the instruction is chosen such that the stuck
faults have the same value as the instruction stored in the array.

      The Figure shows the data path for writing and reading the
control store array.  Instructions are received from the INPUT DATA
lines and are captured in the WRITE REGISTER.  The output of this
register feeds the array, a COMPLEMENT function, and a NOT COMPARE
function.  The output of the COMPLEMENT function is another input to
the WRITE REGISTER.  The output of the array drives another
COMPLEMENT function, and the output of this COMPLEMENT function feeds
the READ REGISTER.  The output of the READ REGISTER feeds both the
OUTPUT DATA lines and the NOT COMPARE function.  Finally, the output
of the NOT COMPARE function is an ERROR signal to the state machine.

      Each instruction has 32 data and 3 parity bits.  The 36th bit
(bit number 35) of each array word is used to provide the polarity
control function.  This bit, cal...