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Browse Prior Art Database

Memory-Mapped Interrupt Acknowledge on PowerPC

IP.com Disclosure Number: IPCOM000114743D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Curry, SE: AUTHOR [+5]

Abstract

Disclosed is a method to interface a PowerPC* processor with a PCI bus for interrupt cycles.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Memory-Mapped Interrupt Acknowledge on PowerPC

      Disclosed is a method to interface a PowerPC* processor with a
PCI bus for interrupt cycles.

      The PCI defines an interrupt acknowledge cycle on the PCI bus.
However, the PowerPC architecture has no such cycle.  The two may be
interfaced with logic implemented in PowerPC systems as described
below.

      When an interrupt controller has a prioritized interrupt, it
signals the CPU-to-PCI bridge, which in turn signals the PowerPC CPU
to interrupt (Figure).

      The CPU does a load byte instruction of a predefined
memory-mapped address.  The CPU-to-PCI bridge decodes this real
address and creates a PCI interrupt acknowledge cycle.  Next, the
interrupt controller supplies an eight-bit data quantity on the PCI
bus.  The CPU-to-PCI bridge passes the eight bits of data to the CPU
as the results of the load byte instruction and concludes the cycle.
The system software then uses the eight-bit data to select a BRANCH
vector.
  *  Trademark of IBM Corp.