Browse Prior Art Database

Efficient Reorganization of On-Chip Digital Signal Processor Memory for External Expansion

IP.com Disclosure Number: IPCOM000114748D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 4 page(s) / 90K

Publishing Venue

IBM

Related People

Dwin, D: AUTHOR [+3]

Abstract

Digital Signal Processors (DSPs) are a specialized class of processors that typically employ a Harvard architecture memory organization. This arrangement calls for separate physical memory arrays for Instruction Store (IS) and Data Store (DS). Single chip implementations of DSPs often include on-chip memory arrays for IS and DS. These implementations also often provide for the attachment of additional external memory chips to the IS and DS buses through expansion pins to increase total available memory. However, off-chip expansion typically requires the presence of address and data buses for both IS and DS on the expansion pins. This is a considerable number of extra pins which leads a more expensive package.

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Efficient Reorganization of On-Chip Digital Signal Processor Memory
for External Expansion

      Digital Signal Processors (DSPs) are a specialized class of
processors that typically employ a Harvard architecture memory
organization.  This arrangement calls for separate physical memory
arrays for Instruction Store (IS) and Data Store (DS).  Single chip
implementations of DSPs often include on-chip memory arrays for IS
and DS.  These implementations also often provide for the attachment
of additional external memory chips to the IS and DS buses through
expansion pins to increase total available memory.  However, off-chip
expansion typically requires the presence of address and data buses
for both IS and DS on the expansion pins.  This is a considerable
number of extra pins which leads a more expensive package.

      Disclosed is a technique for re-organizing on-chip memory
arrays to obtain maximum benefit from them when expanding memory
using additional off-chip memory while also minimizing the number of
pins and hence total package size required for a DSP chip with
external memory expansion capability.

The technique employed is as follows:
  1.  Provide off-chip memory expansion pins (address and data buses)
       for only ONE of the memory arrays.  If the arrays are of
unequal
       word size, choose the array with the WIDER word for off-chip
       expansion.
  2.  Build the on-chip IS and DS memory arrays out of smaller blocks
       and employing switching/multiplexing logic to reorganize the
       blocks into a single memory array for the non-expanded memory
       when off-chip expansion is selected according to the following
       method:
        A) Let M = width of first array (DS or IS)
            Let N = width of second array (IS or DS)
            Let X = depth of first array (DS or IS)
            Let Y = depth of second array (IS or DS)
        B) Assume M <= N and let K=N-M
'        C) Calculate a Packing Factor PF = INT((M/K)+0.5) (where K >
0)
                                          = 0              (where K =
0)
        D) The first array (M by X) will not be expanded externally
            but will have the memory cells of the second array (N by
Y)
     ...