Browse Prior Art Database

Precise Interrupts on Imprecise Error Conditions

IP.com Disclosure Number: IPCOM000114751D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Peterson, JC: AUTHOR [+3]

Abstract

Disclosed is a means to enable a PowerPC* processor to take a precise interrupt when normally an imprecise interrupt would be taken. This increases the likelihood of recovery from a system error.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 60% of the total text.

Precise Interrupts on Imprecise Error Conditions

      Disclosed is a means to enable a PowerPC* processor to take a
precise interrupt when normally an imprecise interrupt would be
taken.  This increases the likelihood of recovery from a system
error.

      In the desktop PowerPC system, whenever a parity error or other
system error is detected, a TEA# signal (CPU transfer error
acknowledge) is driven to the processor.  This causes the processor
to take an imprecise interrupt, which means that software is not
allowed any chance to recover on any system error.

      The disclosed invention will allow software the chance to
recover and will protect vital data by preventing the system from
operating on bad or corrupted data.

      In this invention, a precise interrupt is taken during a
cycle in which a TEA# signal would normally be driven.  This is
accomplished by:
  1.  trapping the error,
  2.  asserting INT (CPU interrupt),
  3.  allowing only the interrupt acknowledge cycle to complete,
  4.  counting the number of cycles before the interrupt acknowledge
       cycle to TEA# for "hung" systems,
  5.  TEA# cycles to the processor if the interrupt acknowledge cycle
       cannot complete.

      In the disclosed invention, an INT_ signal is driven into the
processor rather than TEA# or checkstop.  In addition, this system
sets a bit to latch what type of error condition occurred and latches
the address of the error.

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