Fast Instruction Decode for Code Emulation on Reduced Instruction Set Computer/Cycles Systems
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Imming, KC: AUTHOR [+4]
AbstractDisclosed are the object code emulation hardware assists used to optimize the opcode fetch and subsequent multi-way branch needed to decode the instruction type on a Reduced Instruction Set Computer/cycles (RISC) processor.
Fast Instruction Decode for Code Emulation on Reduced
Set Computer/Cycles Systems
the object code emulation hardware assists used
to optimize the opcode fetch and subsequent multi-way branch needed
to decode the instruction type on a Reduced Instruction Set
Computer/cycles (RISC) processor.
instruction fetching and decoding on RISC systems
is accomplished using the following sequence of instructions.
In the above
sequence, the Load Half and Zero (LHZ) instruction
fetches the object code instruction into GPR 31. The Rotate Left
Double and Insert Mask Immediate (RLDIMI) instruction is used to
compute the address that will later be used for instruction decoding.
The Move To Special Purpose Register (MTSPR) loads the Link Register
(LR) with the calculated address. Finally, the Branch Conditional on
Link Register (BCLR) instruction fetches the target emulation code
using the computed address contained in the LR.
is significantly improved by architecting two new
instructions to assist in the instruction fetching and decoding.
the new instructions, the code sequence is optimized as follows:
The Load and
Compute Address Halfword (LCAHZ) instruction
fetches the object code instruction into GPR 31 and loads the
Computed Branch Register (CBR) with the instruction Opcode as a side
effect. The Branch Conditional on CBR (BCCBR) using the high or low
nibble of the CBR as an offset from the Count Register (CTR), forms
the address for fetching the target emulation code.
extended mnemonics, lcahz and lcahzu, are provided that
are equivalent to lhz and lhzu respectively, but serve to emphasize
where the CBR loading is required by the code. This is provided as a
coding aid only. The hardware updates the CBR on every execution of
an lhz or lhzu instruction, since no mechanism is provided to specify
when the CBR loading function is required.
Branch Address Register (CBR) is an 8-bit
register. It is used as an offset from the CTR for the target of a
new branch conditional instruction to provide the branch target
address for the bccbr instruction. The load of the CBR is performed
as a side effect of the lhz and lhzu instructions when they are
executed with GPR 31 as the target of the load.
if RT=31 then
CBR < MEM(EA,1)
In the case
where the lhz or lhzu causes an Alignment