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Single-Error Correction and Double-Error Detection Method

IP.com Disclosure Number: IPCOM000114778D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Chen, CL: AUTHOR

Abstract

This article describes rapid generation of check bits, a rapid error correction of single-errors and error detection of double-errors with simple error correction circuits with a (44, 32) Single-Error Correction (SEC)-Double-Error Detection (DED) code.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Single-Error Correction and Double-Error Detection Method

      This article describes rapid generation of check bits, a rapid
error correction of single-errors and error detection of
double-errors with simple error correction circuits with a (44, 32)
Single-Error Correction (SEC)-Double-Error Detection (DED) code.

      The error-correction and error-detection scheme is applicable
to the class of weight-3 column SEC-DED codes that are described
hereinafter.

      Fig. 1A shows the parity-check matrix of a (44,32) SEC-DED
code.  The value of check bit Ci is generated by the XOR of the data
bits whose positions are marked with 1's in the i-th row of the
matrix.  Notice that C1, C2, C3, C4 represent the byte parity checks
for the 4 data bytes, and each check bit is the XOR of a set of 8
data bits.  There are only 3 levels of logic delay in the generation
of check bits, which is the same as the conventional byte parity
check.

      The first step in error correction and error detection is the
generation of the 12-bit syndrome S.  Syndrome Si is the XOR of the
received check bit Ci and the check bit Ci generated from the
received data bits.  The circuit for single-error correction and
double-error detection are shown in Fig. 1B.  Each data bit is
corrected simply with a 2-way XOR gate and a 3-way AND gate.  For
example, data bit 1 is the XOR of the received data bit 1 and the AND
of the syndrome bits 1, 5, 9 that correspond to the ones of the first
column of the parity-check matrix.  In g...