Browse Prior Art Database

Verification of Circuit Model and Logic Model of a Chip

IP.com Disclosure Number: IPCOM000114790D
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Jaber, T: AUTHOR [+3]

Abstract

Disclosed is a technique that uses built-in self-test architecture to guarantee the logical equivalency of circuit model and logic model of a chip.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Verification of Circuit Model and Logic Model of a Chip

      Disclosed is a technique that uses built-in self-test
architecture to guarantee the logical equivalency of circuit model
and logic model of a chip.

      In a chip design methodology, the logical behavior of a chip is
normally expressed in DSL, and the chip physical behavior is normally
in transistor schematics.  In most cases, these transistor schematics
reflect many, very small, segments of the total chip circuitry.
Stitching these circuits together is not a always an easy task and
the integrity of the total circuit as a result of the integration of
the individual circuits segmenta must be checked and tested.

      To guarantee the logical equivalency between DSL and circuit
schematics of a chip, a technique with the following procedure can be
used:
  o  A chip logic behavioral model needs to be generated and
described
      in DSL language or any other language used by the logic
designers
      for logic entry.  This requires a DSL model for every circuit
      used by the designers.  In particular, latch circuits must be
      modeled in DSL DESBLOs (design blocks) that not only describes
      how the latch behaves functionally, but also how the latch
      behaves in scan mode and under all various conditions of
clocking
      control (for example, clock stopping).
  o  A logical description of the circuit transistor schematics is
      required.  This can be done by hand (a designer describes the
      circuit logic behabior based on his/her understanding of the
      circuit schema...