Browse Prior Art Database

Self-Timed Hit Circuit for a Content Addressable Memory

IP.com Disclosure Number: IPCOM000114806D
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Aipperspach, AG: AUTHOR [+4]

Abstract

Described is a method of generating a NAND-like compare for a Content Addressable Memory (CAM) by using the DOT-NOR and self-timed activated circuit.

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Self-Timed Hit Circuit for a Content Addressable Memory

      Described is a method of generating a NAND-like compare for a
Content Addressable Memory (CAM) by using the DOT-NOR and self-timed
activated circuit.

      The following circuit uses the concept of a self-timed signal
that tracks the performance of the worse case MISS line and allows
the HIT circuits to operate properly.  The BICMOS case is discussed
here, but a similar version for CMOS is also possible.  Fig. 1 shows
a rough block diagram of the CAM's critical path.  The KEY inputs are
NANDed with the clock and the true and compliment compare signals are
bussed to the CAM cells.  The disclosed approach would NAND together
the true and compliment compare signals of the farthest most KEY bit
to produce a timing signal.  The timing signal shown as node DELAY is
loaded with dummy loads that match the loading on the MISS/HIT lines.
The DELAY signal is then NAND-ed and NOR-ed with the clock to produce
the two nodes ACTV and PCHG.  The timing relation between these two
signals is shown in Fig. 2.  The PCHG (precharge) signal is used to
initialize the  MISS/HIT lines and the MATCH output.  The ACTV
(activate) signal is used to trigger the MATCH output to go high when
all the MISS/HIT lines have had a change to evaluate.  The timing of
the DELAY signal must be long enough to insure all the MISS/HIT lines
have had a change to evaluate, but not so long as to adversely affect
performance.