Browse Prior Art Database

Error Detection Scheme for Content Addressable Memory

IP.com Disclosure Number: IPCOM000114815D
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 4 page(s) / 60K

Publishing Venue

IBM

Related People

Aipperspach, AG: AUTHOR [+4]

Abstract

Described is a minimum sized detection scheme for multiple matches in a wide Contents Addressable Memory (CAM).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 81% of the total text.

Error Detection Scheme for Content Addressable Memory

      Described is a minimum sized detection scheme for multiple
matches in a wide Contents Addressable Memory (CAM).

      For large CAMs (64 words or more), it is fairly difficult to
detect quickly if more then one of the locations matches an incoming
key.  The following approach shows an efficient use of the OR tree
stages already used in the MATCH signal (part of the base function)
to produce the desired output.

      Fig. 1 shows a clocked dynamic 4-OR circuit (OR) used to
produce the MATCH signal.  Fig. 2 shows a clocked dynamic
error-detect circuit (ER) which is a key building block to the
multiple match detection scheme.  The inputs to this circuits are
assumed initially low.  The function of the circuit is to produce a
logical "1" at the output when two or more inputs go to a "1" during
evaluation.  This is the multiple match or ERROR condition.  Fig. 3
shows a clocked dynamic 4-OR/error-detect circuit (OER) which is also
a key building block.  The function of this block is similar to the
ER circuit but with the four additional inputs which force the ERROR
state on the output if any one of these goes high during the
evaluation phase.

      Fig. 4 shows how both the ERROR and MATCH signals are generated
in parallel for a large width CAM.  At the initial stage, the CAM
locations are divided in groups of four.  A local MATCH and ERROR
signal are produced for each group.  The second stag...