Browse Prior Art Database

Balancing Clock Trees Across Different Chips

IP.com Disclosure Number: IPCOM000114829D
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Johnson, DWJ: AUTHOR

Abstract

A method for balancing clock tree delays across chips of different sizes and utilizing different technologies.

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This is the abbreviated version, containing approximately 66% of the total text.

Balancing Clock Trees Across Different Chips

      A method for balancing clock tree delays across chips of
different sizes and utilizing different technologies.

      In a synchronous system, clocks need to arrive at latches
simultaneously.  If two chips have different internal delays for the
clock from the pin to the latch, the skew between the clocks causes
timing degradation.

      This delay difference in the clock trees results from either a
difference in the architecture of the tree (different technologies
have different books available) or differences in size and loading of
the trees.

      For two chips in the same technology, but having a greatly
different latch count, the "natural" tree would be a much different
size for the two chips and therefore have much different delays.  By
taking the tree of the larger chip and using the same structure for
the smaller chip, the same tree is maintained and therefore the same
delay.

      The design first starts by having the best possible tree for
the larger chip, since this determines the minimum delay possible.
Also, it is always possible to increase the delay in the smaller
chip's tree, but not to decrease the delay in the larger chip's tree
since it is by definition the smallest achievable delay.

      Since the tree is "too large" for the smaller chip, using it
intact would mean that there are more drivers for the latches than
there are for the larger chip.  The difference in fanout, and...