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High Speed Complimentary Metal Oxide Semiconductor Input/Output Circuits

IP.com Disclosure Number: IPCOM000114830D
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 4 page(s) / 72K

Publishing Venue

IBM

Related People

Cao, TA: AUTHOR [+2]

Abstract

High-performance in a machine requires the delay of Off-Chip Drivers (OCD) and Off-Chip Receivers (OCR) be minimum. A significant portion of delay budget of OCD/OCR is due to pre-drive stage and enable/inhibit portion. This disclosure proposes a CMOS inverting OCD/inverting OCR pair in which enable/inhibit is incorporated into output stage to minimize delay.

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High Speed Complimentary Metal Oxide Semiconductor Input/Output Circuits

      High-performance in a machine requires the delay of Off-Chip
Drivers (OCD) and Off-Chip Receivers (OCR) be minimum.  A significant
portion of delay budget of OCD/OCR is due to pre-drive stage and
enable/inhibit portion.  This disclosure proposes a CMOS inverting
OCD/inverting OCR pair in which enable/inhibit is incorporated into
output stage to minimize delay.

      Fig. 1 shows the schematic of the OCD.  The main part of OCD is
output e stage devices QP1 and QN2, which are usually large devices.
The driver input is fed to the gates of transistor QP1 and QN2
through resistors RP1 and RN1.  For PFET device QP1, RP1, RP2, and
equivalent resistance value of QP3 (RQP3) act as volatge divider.
The values of these resistors are designed such that the ratio (RQP3
+ RP2)/(RQP3 + RP2 + RP1) >= ratio of Vtp/Vdd, where Vtp is the
threshold voltage of PFET.  Similarly, for NFET device QN2, the
values
of resistors RN1, RN2, and equivalent resistance value of QN4 (RQN4)
are
chosen such that the ratio (RQN4 + RN2)/( RQN4 + RN2 + RN1) </= the
ratio
of Vtn/Vdd, where Vtn is the threshold voltage of NFET.

      In normal operation, devices QP3 and QN4 are turned off.  Data
input passes through resistors RP1 and RN1 and is inverted by output
stage large devices.  When OCD is tristated, devices QP3 and QN4 are
turned on.  The voltage at node 1 (Fig. 1) varies within the range of
(vdd, vdd-Vtp).  Since the Vgs of QP1 is less than the threshold
voltage of PFET Vtp, the output stage PFET QP1 is turned off.  On the
other hand, the voltag...