Browse Prior Art Database

Real Time Chip Monitor Capability

IP.com Disclosure Number: IPCOM000114831D
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+4]

Abstract

Unlike clock synchronous processor chips, I/O Channel Controllers (IOCC) typically contain multi-clocked state machines and asynchronous logic. As IOCC designs become more aggressive, with overlapped/background operations and pipelined transfers, the observability of internal multi-clocked/asynchronous operations becomes a complex task. This paper describes a method of observing these internal chip nets in a real time fashion.

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This is the abbreviated version, containing approximately 87% of the total text.

Real Time Chip Monitor Capability

      Unlike clock synchronous processor chips, I/O Channel
Controllers (IOCC) typically contain multi-clocked state machines and
asynchronous logic.  As IOCC designs become more aggressive, with
overlapped/background operations and pipelined transfers, the
observability of internal multi-clocked/asynchronous operations
becomes a complex task.  This paper describes a method of observing
these internal chip nets in a real time fashion.

      During the initial design of a complex,
multiclocked/asynchronous chip, it is reccommended that the structure
in the Figure be added to the design.  Each INTERNAL NETS bus
contains a specific set of internal signals which can be observed,
relative to each other.  The +NEXT signal, when pulsed, increments
the mux selector thus allowing a different set of INTERNAL NETS to be
observed.  The ASYNCHRONOUS COUNTER is reset at power on, and
increments during each +NEXT pulse.  (The details of this
ASYNCHRONOUS COUNTER is beyond the scope of this paper).  This allows
one to observe any set of INTERNAL NETS in a real time fashion, thus
providing the ability to quickly debug complex asynchronous problems.
Also, this allows one to observe the relative speeds of asynchronous
internal races and functional pulses.  This may further accellerate
design and performance optimizations during the second "pass" of the
design.  Finally, in order to reduce overall product costs, it is
reccommended that this e...