Browse Prior Art Database

Multi-Dimension Digital Phase Lock Loop

IP.com Disclosure Number: IPCOM000114835D
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 4 page(s) / 122K

Publishing Venue

IBM

Related People

Woodman Jr, GR: AUTHOR

Abstract

Fault tolerant groups of processors or controllers require independent oscillators for their clocks in order to guard against any single point of failure. There is great value, however, in terms of simplicity of design and reduced logic requirement for such systems if they can be run synchronously.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Multi-Dimension Digital Phase Lock Loop

      Fault tolerant groups of processors or controllers require
independent oscillators for their clocks in order to guard against
any single point of failure.  There is great value, however, in terms
of simplicity of design and reduced logic requirement for such
systems if they can be run synchronously.

      One form of the all Digital Phase Lock Loop described in this
invention performs the frequency locking/phase lock loop function by
adding a delay element as needed to keep the oscillator signals in
phase and functionally selects the slower of two oscillators as the
"Master".  The topology of the configuration dictates that only two
units can be so connected, thus the application of the function is
limited to situations that only require two synchronized units.

      The procedure of adding delay is desirable from a logic point
of view, since most logic designs are most sensitive to the minimum
time between clocked events ("short path problems").  Adding delay to
maintain clock sync means some clock periods will be sightly longer
than others, but, never shorter.  Logic design using such a function
must, however, be insensitive to "long path" problems.

      Performing the phase locking function by all digital logic also
requires that the control of the logical elements not be effected by
analog signal limitations.  It is possible to add two or more phase
comparators, that by nature are sensitive analog/logic elements, and
use them to control the delay add logic function.  Such phase
comparators can be structured to each select the slower reference
signal and thus in concert will select the slowest reference of the
group.  Logic elements can also conveniently bound the selection or
inclusion of reference/phase comparators to be used in the
synchronization procedure.  Simple logic gates permit the addition or
deletion of reference paths without impacting the accuracy of the
comparators or the precision of the phase locking operation.

      Fig. 1 illustrates the concept of all digital phase locking
adjacent pairs of units in vector arrangements such as might be used
for a vector processor.  The configuration provides a synchronization
pair for each communication connection between processors, and thus
provides the needed precision of synchronization at the required
location.  Each of the processors has its own independent crystal
oscillator and thus provides no single point of failure for the
clocking system.  The natural bias of the pair operation will select
the slowest cryst...