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Browse Prior Art Database

Enhanced Access Chip Footprint

IP.com Disclosure Number: IPCOM000114862D
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Kresge, JS: AUTHOR [+3]

Abstract

Disclosed is a chip footprint and complementary carrier design, which simplifies the manufacture of flip-chip carriers.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Enhanced Access Chip Footprint

      Disclosed is a chip footprint and complementary carrier design,
which simplifies the manufacture of flip-chip carriers.

      The design and production of flip-chip carriers such as
laminate Single Chip Modules (SCM-L), and large direct chip attach
planars is complicated by the need for fine lines and vias.  Escaping
signal connection from flip-chip die typically requires line widths
of 1 mil or less, and via pitches of 10 mils or less.  These features
are more demanding than general laminate processes can produce at
high yield, driving higher cost to the final product.  This
disclosure describes a modified full array chip footprint, and
carrier design, which allow direct chip attach to 20 and 25 mil
carrier via grids using 2 and 3 mil lines for escape.  This design
provides a significant number of signal connections to the chip, and
eliminates the need for fine line and via escape.

      A modified full array chip footprint 1 is shown in the Figure.
Rows of signal C-4s 2 are interleaved with rows of power and ground
C-4s 3.  The signal rows are depopulated at every other position to
attain a signal C-4 pitch twice that of the basic chip C-4 pitch.  If
the basic chip C-4 pitch is designed at 10 mils, the signal C-4s will
be on a 20 mil grid.  The power and ground C-4s are maintained at
full density to ensure proper chip power distribution.  With this
configuration, 25% of the total C-4 count could be used for signal
connection.  Given a full array 14.7mm chip, this would provide 784
signal I/O on a 20 mil pi...