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High Efficiency Boost Converter with Synchronous Clock

IP.com Disclosure Number: IPCOM000114869D
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 106K

Publishing Venue

IBM

Related People

Duncan, MA: AUTHOR [+2]

Abstract

A circuit topology for a DC/DC power converter is disclosed. The converter achieves high power efficiency and maintains stability from zero to the maximum load current at a fixed chopping frequency while operating entirely in the continuous inductor current mode.

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This is the abbreviated version, containing approximately 51% of the total text.

High Efficiency Boost Converter with Synchronous Clock

      A circuit topology for a DC/DC power converter is disclosed.
The converter achieves high power efficiency and maintains stability
from zero to the maximum load current at a fixed chopping frequency
while operating entirely in the continuous inductor current mode.

      The circuit achieves both high efficiency and continuous mode
operation from zero to maximum output current by means of PASS FET 5
and its control technique.  The starting circuitry and gate drive
voltage boost circuitry are not included in this disclosure.
Although the Figure depicts a direct duty cycle control block 22, the
technique is also applicable to current mode control by properly
modifying the control block.

      For the following description, assume the initial state of the
circuit is with BOOST FET 4 ON and PASS FET 5 OFF and that gates 8
and
12 also contain FET drivers.  The CLOCK IN signal 1 drives both
the sawtooth generator 2 and the FET DRIVER LATCH 3.  The clock
signal has two functions, first to synchronize the switching to an
external clock, and second to limit the duty cycle of boost FET 4.
When the clock signal 1 changes from HIGH to LOW, it causes the
sawtooth generator 2 to output a negatively sloped voltage ramp at
signal VSAW.  The negative transition of clock signal 1 also causes
the -RESET line 7 of FET DRIVER LATCH 3 to switch LOW and the +S
input of the JITTER LATCH 6 to switch HIGH which causes the -SET
line of the FET DRIVE LATCH 3 to also switch HIGH.  (The JITTER
LATCH 6 has positive active SET and RESET inputs with an overriding
SET.)  This combination of signals switches the NAND gate 8 LOW,
which begins to turn BOOST FET 4 OFF.  (The FET DRIVER LATCH 3 has
negative active SET and RESET inputs with an overriding RESET.)  The
gate of BOOST FET 4 has intrinsic capacitance that must be
discharged through resistor 13 before the FET 4 actually turns OFF.
Resistor 13 represents the output resistance of the FET DRIVER LATCH
3 and any external circuit resistance used to protect the driver 3
from overcurrent.  This results in a negative ramp at gate voltage 9.
Comparator 10 senses the gate voltage 9, and its output 11 remains
LOW until the gate voltage 9 becomes less than the reference voltage
VREF GATE B.  During the time when output 11 is LOW, the output of
the NAND gate 12 is also forced LOW, keeping PASS FET 5 OFF.  After
gate voltage 9 falls below voltage VREF GATE B, the output of
comparator 10 switches HIGH, which switches the outp...