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Hardware Timer Comparison for Isochronous Channel Events

IP.com Disclosure Number: IPCOM000114883D
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-30

Publishing Venue

IBM

Related People

Parker, TE: AUTHOR

Abstract

This mechanism allows a hardware take action on Isochronous Channels based on a comparison of the P1394 Bus Cycle Timer and a software programmed time value for each Isochronous Channel. The actions it can accomplish for Transmit Channels are: o Start transmitting packets when this Cycle number is reached o Stop transmitting packets when this Cycle number is reached o Pause while transmitting packets when this Cycle number is reached o Resume (after Pause) when this Cycle number is reached

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 15% of the total text.

Hardware Timer Comparison for Isochronous Channel Events

      This mechanism allows a hardware take action on Isochronous
Channels based on a comparison of the P1394 Bus Cycle Timer and a
software programmed time value for each Isochronous Channel.  The
actions it can accomplish for Transmit Channels are:
  o  Start transmitting packets when this Cycle number is reached
  o  Stop transmitting packets when this Cycle number is reached
  o  Pause while transmitting packets when this Cycle number is
reached
  o  Resume (after Pause) when this Cycle number is reached

The actions it can accomplish for Receive Channels are:
  o  Start receiving packets when this Cycle number is reached
  o  Stop receiving packets when this Cycle number is reached
  o  Pause while receiving packets when this Cycle number is reached
  o  Resume (after Pause) when this Cycle number is reached
  o  Start receiving packets on the first SOS received (in the SY
      field of the packet header) after this Cycle number is reached
  o  Stop receiving packets on the first SOS received (in the SY
field
      of the packet header) after this Cycle number is reached
  o  Pause while receiving packets on the first SOS received (in the
      SY field of the packet header) after this Cycle number is
reached
  o  Resume (after Pause) on the first SOS received (in the SY field
      of the packet header) after this Cycle number is reached

      It reuses the Arithmetic Logic Unit (ALU) and dataflow
described below to perform arithmetic operations which determine
whether or not the value software has programmed in the "Isochronous
Transmit/Receive Seconds/Cycle Count Register" for that Transmit or
Receive Isochronous channel is equal to the current Seconds/Cycle
Count field of the "Cycle Timer" (a P1394 timer/counter register).

      This invention was developed for use in a module which performs
the Link function for the IEEE p1394 High Performance Serial Bus and
provides an interface between the physical layer chip for this serial
bus and the PCI bus.

      This invention is designed to support the Isochronous Channel
controls proposed in the current draft of the ANSI X3T9.2 SCSI-3
Serial Bus Protocol and the draft IEEE P1394 High Performance Serial
Bus.  The implementation is designed to reuse the ALU and dataflow
described in Fig. 1 and implemented in the design of the module.

Note: The SHIFT A function of the ALU performs a left shift on the
high order 8 bits (bits 31 - 24) of INPUT A by one bit with either
bits 31, 30, 29, or 28 of INPUT A being circularly shifted into bit
24 of the ACCUMULATOR based on the pattern length field (bits 23 and
22 of INPUT A).  Bits 23 - 16 of INPUT A are propogated to the
ACCUMULATOR unshifted.

      For each channel for which software has requested that an
ACTION (i.e., Start, Stop, Pause, or Resume) occur at (or on SOS
following) at particular Cycle Timer value, the hardwar...