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Compact Method for Updating Timebase and Decrementer Registers

IP.com Disclosure Number: IPCOM000114890D
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

McDonald, TC: AUTHOR [+3]

Abstract

The 604 processor uses two separate facilities to provide timing functions for the system. The timebase is a 64 bit register that counts upward at constant frequency. The decrementer is a 32 bit register that counts downward at the same frequency. They can be used by the system to keep system to keep track of the current time of day, signal interrupts after a certain period of time, or determine how much time elapses between certain events.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 56% of the total text.

Compact Method for Updating Timebase and Decrementer Registers

      The 604 processor uses two separate facilities to provide
timing functions for the system.  The timebase is a 64 bit register
that counts upward at constant frequency.  The decrementer is a 32
bit register that counts downward at the same frequency.  They can be
used by the system to keep system to keep track of the current time
of day, signal interrupts after a certain period of time, or
determine how much time elapses between certain events.

      The standard method of updating the timebase and decrementer
would require a 64 bit incrementer for the timebase and a 32 bit
decrementer for the decrementer.  Since incrementers and decrementers
are large compared to other components such as muxes and registers, a
method is desired that accomplishes the timebase/decrementer function
using smaller components.

      A method is disclosed that uses a 4-state state machine and a
single 32 bit incrementer to update the timebase and the decrementer.
The method uses a special state to synchronously enable or disable
each timer facility and keep their counts coherent.

      This method is possible since the 604 timer facility frequency
is the system clock divided by four.  With the fastest relative
system clock (1:1 bus mode), the timers will spin at a frequency
equal to the processor clock divided by four.  This allows four
cycles to be used to update all of the timer facilities.

The state ma...