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Data Address Conversion for Hard Disk Drive with AT Interface

IP.com Disclosure Number: IPCOM000114892D
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 78K

Publishing Venue

IBM

Related People

Murakami, M: AUTHOR [+3]

Abstract

Disclosed is a circuit for converting data address of Hard Disk Drive (HDD) with AT interface from logical Cylinder, Head and Sector (CHS) to Logical Block Address (LBA). As shown in the Figure, this circuit automatically converts CHS issued from a host system to LBA which is proper for HDD by using a multiplier and an adder. Therefore the performance of data transfer is improved more than Micro Processing Unit (MPU) converts from CHS to LBA.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Data Address Conversion for Hard Disk Drive with AT Interface

      Disclosed is a circuit for converting data address of Hard Disk
Drive (HDD) with AT interface from logical Cylinder, Head and Sector
(CHS) to Logical Block Address (LBA).  As shown in the Figure, this
circuit automatically converts CHS issued from a host system to LBA
which is proper for HDD by using a multiplier and an adder.
Therefore
the performance of data transfer is improved more than Micro
Processing
Unit (MPU) converts from CHS to LBA.

The equation of the CHS-LBA conversion is as follows:
  Start LBA = {CYL x (HDCNT+1) + HEAD} x TRKLEN + (SEC-1)
  Last LBA = Start LBA + (SECCNT-1)
  CYL : Start cylinder number
  HEAD : Start head number
  SEC : Start sector number
  HDCNT : Maximum head number
  TRKLEN : Maximum sector number
  SECCNT : Transfer sector number

      CYL, HEAD and SEC are parameters issued by a host.  HDCNT,
TRKLEN and SECCNT are parameters which HDD has as logical parameters.
The Figure shows the example of this circuit.  The mark "/" in the
Figure indicates the bit width of its signal.  For example, "/8"
indicates that its signal is 8bits.  Alphabets "a-b" and "c-g" are
select and gate signals respectively to calculate the above equation.

      At first, HDCNT+1 is loaded into Start LBA Register through
SEL1.  And then CYL x (HDCNT+1) is calculated.  In this time "d"
becomes active, two inputs to 28bit Adder are added, the left input
of SEL2 (Carry and upper 27bit of 28bit Adder output) is selected a...