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High Speed/Low Power Stand-Alone or 3-State Receiver for Mixed Voltage Applications

IP.com Disclosure Number: IPCOM000114919D
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Dreps, DM: AUTHOR [+2]

Abstract

In Conventional CMOS receiver design the switching threshold is set by the ratio of the N and P widths. One may simply scale these parameters to set a 1.2 volt TTL threshold or a Vdd/2 threshold for CMOS applications. In LVTTL the driver only has to drive up to 2.4 volts. For 2.5 volt CMOS the driver has to insure an up level of about 2.25 volts. If the receiver has a Vdd of 3.0 volts or even higher (3.8 volts) the P-FET in the conventional design never shuts off. This is due to the fact that the incident up level is less than Vdd-Vtp. When this happens the input stage PFETs and NFETs are both on. Typically, the input stage is sized with reasonably big input devices because the block delay is faster and the driver is not very sensitive to .1 to 2pF of additional gate load.

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High Speed/Low Power Stand-Alone or 3-State Receiver for Mixed Voltage
Applications

      In Conventional CMOS receiver design the switching threshold is
set by the ratio of the N and P widths.  One may simply scale these
parameters to set a 1.2 volt TTL threshold or a Vdd/2 threshold for
CMOS applications.  In LVTTL the driver only has to drive up to 2.4
volts.  For 2.5 volt CMOS the driver has to insure an up level of
about 2.25 volts.  If the receiver has a Vdd of 3.0 volts or even
higher (3.8 volts) the P-FET in the conventional design never shuts
off.  This is due to the fact that the incident up level is less than
Vdd-Vtp.  When this happens the input stage PFETs and NFETs are both
on.  Typically, the input stage is sized with reasonably big input
devices because the block delay is faster and the driver is not very
sensitive to .1 to 2pF of additional gate load.  The higher the
transconductance of the input stage FETs the higher the DC current
for the conditions described.  The DC current will typically be over
a milliamp/receiver for these conditions.  Minimizing device sizes in
the receiver input stage causes the block delay to increase which is
the wrong answer.

      The following shows a topology that limits the dc current to
about 50 microamps/receiver, results in no additional block delay and
is compatible with all current cmos processes and conventional cmos
circuit design techniques.  The disclosed solution is compatible with
2.4 volt LVTT...