Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Implementation Verification Program C Monitoring Strategy for Implementation Specific Verification

IP.com Disclosure Number: IPCOM000114920D
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 137K

Publishing Venue

IBM

Related People

Keist, R: AUTHOR [+2]

Abstract

One of the major difficulties in the verification of increasingly more complex microprocessor designs is the ability to exercise all implementation specific test vectors in a reasonable amount of time. Historically, microprocessor verification has been a two pronged approach, relying on both randomly generated and manually targeted test vectors to provide a complete verification strategy. Further, the design is typically broken down into functional units and implementation specific plans (Implementation of Verification Program or "IVP") that outline all the necessary test scenarios needed to be exercised to guarantee the functionality of a given unit. The completion of all plans is essential to insure the quality of the overall design.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 45% of the total text.

Implementation Verification Program C Monitoring Strategy for Implementation
Specific Verification

      One of the major difficulties in the verification of
increasingly more complex microprocessor designs is the ability to
exercise all implementation specific test vectors in a reasonable
amount of time.  Historically, microprocessor verification has been a
two pronged approach, relying on both randomly generated and manually
targeted test vectors to provide a complete verification strategy.
Further, the design is typically broken down into functional units
and implementation specific plans (Implementation of Verification
Program or "IVP") that outline all the necessary test scenarios
needed to be exercised to guarantee the functionality of a given
unit.  The completion of all plans is essential to insure the quality
of the overall design.  However, due to the complexity and volume of
test scenarios, these IVP plans typically include, it would be
impossible to manually write all the necessary test vectors within
the time limitations of the given project.

      The solution to this problem is to provide a means by which the
verification engineer can adequately measure which areas of the IVP
plan need to be manually targeted versus which areas are getting
exercised by the random testing strategy.  Given the fact that
randomly generated test vectors cannot adequately test units 100%
within a design, the need for manually written test vectors will not
disappear.  However, by having a monitor feedback system, the
verification engineer can efficiently target areas that will not be
tested randomly, while not duplicating any effort in creating test
vectors that are easily verified by random testing.  Furthermore, by
employing a feedback strategy, the verification engineer can analyze
and adjust the random generation biasing to target more specific
areas within the IVP plan.  If certain areas were still not getting
exercised, the verification engineer could begin manually targeting
these areas in parallel to this monitor strategy.

      Following is a description of the IVPC monitor methodology.  A
flow chart illustrates each step of the process.
  1.  Define what is to be monitored - This is the first step in the
       process.  The verification engineer, most likely in
cooperation
       with the design engineers, must define which types of events
are
       of interest in the design.  The engineer must come up with a
plan
       (IVP plan) which will provide sufficient coverage in the
design
       while keeping in mind that it will not be possible to track
every
       possible event and still have a finite number of event
       permutations.
  2.  Create monitor - This step involves the implementation of the
       plan set forth in step 1.  This involves writing an
       Implementation Verification Program C (IVPC) which will act to
       monitor the e...