Browse Prior Art Database

Support Mechanisms for Isochronous Data Control Blocks

IP.com Disclosure Number: IPCOM000114930D
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 135K

Publishing Venue

IBM

Related People

Hoch, GB: AUTHOR [+4]

Abstract

This command chaining control block and data buffer structure achieves the following goals: o Allows data in Isochronous data buffers to be contiguous without regard for P1394 Isochronous packet boundaries or headers. Hardware automatically builds headers for each Transmit packet and strips headers for each Receive packet. o Allows Isochronous Receive/Transmit Data control blocks to reside in physically different (PCI addressable) memory from associated Isochronous Data buffers. o Allows microcode to dynamically append additional Isochronous Receive/Transmit Data control blocks to a chain of control blocks as additional data buffers are made available for Reception/Transmission of Isochronous Data.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 51% of the total text.

Support Mechanisms for Isochronous Data Control Blocks

      This command chaining control block and data buffer structure
achieves the following goals:
  o  Allows data in Isochronous data buffers to be contiguous without
      regard for P1394 Isochronous packet boundaries or headers.
      Hardware automatically builds headers for each Transmit packet
      and strips headers for each Receive packet.
  o  Allows Isochronous Receive/Transmit Data control blocks to
reside
      in physically different (PCI addressable) memory from
associated
      Isochronous Data buffers.
  o  Allows microcode to dynamically append additional Isochronous
      Receive/Transmit Data control blocks to a chain of control
blocks
      as additional data buffers are made available for
      Reception/Transmission of Isochronous Data.
  o  Provides a mechanism for posting of interrupts to microcode as a
      result of fetching particular Isochronous Receive/Transmit
      control blocks.
  o  Minimizes posted interrupts during normal operation.

      This invention was developed for use in a module which performs
the Link function for the IEEE P1394 High Performance Serial Bus and
provides an interface between the physical layer chip for this serial
bus and the PCI bus.  This module is intended for use in all ranges
of portable/laptop computers, desktop computers, and servers which
implement a PCI Local Bus.

      Operation of Receive/Transmit Data Control Block - This
disclosure describes a control block and data buffer structure and
control mechanism used by the Isochronous Receive/Transmit Channels
of the P1934 Serial Bus Controller for accessing data (and control
blocks) residing in PCI Bus Addressable Memory to allow
reception/transmission of this data from/to the 1394 Bus.

Fig. 1 shows the format of the Isochronous Data Buffer Control block.

      This control block format is used to store data into a data
buffer after receiving packets on an Isochronous channel or to fetch
data from a data buffer prior to transmitting packets on an
Isochronous channel.  The module is programmed by software with the
address of the first control block in a chain of control blocks for
an isochronous channel.  Then, when the isochronous channel is
activated, hardware fetches the first control block which in turn
would contain the address of the first data buffer (into which data
for that Isochronous Receive channel is to be stored or from which
data for that Isochronous Transmit channel is to be fetched.

      On Receive Channels, hardware is responsible for removing
isochronous header and CRC information from the Isochronous Data
Packets that it is Receiving from the P1394 Bus and choosing what
packet data to save based on the contents of the Isochronous Channel
Registers previously programmed by software prior to channel
activation.  Hardware stores receive data into that data buffer fr...