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Priority Scheme for Arithmetic Logic Unit and Dataflow Usage by P1394 Isochronous Hardware

IP.com Disclosure Number: IPCOM000114951D
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 161K

Publishing Venue

IBM

Related People

Parker, TE: AUTHOR

Abstract

Disclosed is a mechanism to prioritize the usage of the common dataflow and Arithmetic Logic Unit (ALU), among various state machines implementing P1394 isochronous data transmission and reception, in order to ensure that the highest priority tasks are performed first. Any of these state machines may be ready to use the dataflow and ALU at the same time as any other. This mechanism is part of a circuit chip performing the link function for the IEEE P1394 High Performance Serial Bus. This chip provides an interface between the physical layer chip for this serial bus and the Peripheral Component Interconnect (PCI) bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 45% of the total text.

Priority Scheme for Arithmetic Logic Unit and Dataflow Usage by P1394
Isochronous Hardware

      Disclosed is a mechanism to prioritize the usage of the common
dataflow and Arithmetic Logic Unit (ALU), among various state
machines implementing P1394 isochronous data transmission and
reception, in order to ensure that the highest priority tasks are
performed first.  Any of these state machines may be ready to use the
dataflow and ALU at the same time as any other.  This mechanism is
part of a circuit chip performing the link function for the IEEE
P1394 High Performance Serial Bus.  This chip provides an interface
between the physical layer chip for this serial bus and the
Peripheral Component Interconnect (PCI) bus.

The flowchart shows the method of hardware prioritization among
various usage scenarios.

      In Runs 1 through 4, the Seconds/Cycle Count field of the
hardware Cycle Timer is compared with the software-programmed
"Isochronous Receive Seconds/Cycle Count Register for a channel.  In
run 1, this register is for Receive Channel 0; in run 2, this
register
is for Receive Channel 1; in run 3, this register is for Transmit
Channel
0; and in run 4, this register is for Transmit Channel 1.

      In Runs 5 and 6, the newly programmed value of the "Isochronous
Transmit Synch Period Register" for Transmit Channel 0 and 1,
respectively, is compared to the "Isochronous Transmit Current Synch
Count Working Register" for the same channel.

      In Runs 7 through 10, the newly programmed value of the
"Isochronous Transmit Data Rate B (or C) Register" for a transmit
channel is copied to the "Isochronous Transmit Current Data Size B
(or C) Working Register" for the same transmit channel.  In Runs 6
and 7, this is done for B registers, while in Runs 8 and 10, this is
done for C registers.  In Runs 6 and 8, this is done for Transmit
Channel 0, while in Runs 7 and 10, this is done for Transmit Channel
1.

      In Run 11, a Receive Data Packet operation already started on
Receive Channel 0 or 1 is completed.

      In Runs 12 and 13, Receive Channels 0 and 1, respectively, are
prepared to start receiving data packets by fetching their first
control blocks from PCI addressable storage.

      In Runs 14 and 15, Transmit Channels 0 and 1, respectively, are
prepared to start transmitting data packets by fetching their first
control blocks from PCI addressable storage.

      In Run 16, the transfer of a receive data packet from its FIFO
buffer to PCI bus addressable storage is begun for either Receive
Channel 0 or Receive Channel 1.  If the receive data packet crosses a
buffer boundary, the control block for the next buffer in the chain
is also fetched.  This State Machine operation is complete when the
DMA register(s) is/are set up to perform the data transfer(s) on the
PCI bus.  Another State Machine operation completes the transfer of
the receive data packet.

      In Runs 17 and 18, data is fetched for...