Browse Prior Art Database

On-Chip Programmable Termination Scheme

IP.com Disclosure Number: IPCOM000114953D
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 76K

Publishing Venue

IBM

Related People

Cao, T: AUTHOR [+3]

Abstract

Communication between chips sometimes requires parallel termination. Before the existence of a resistance layer, on-chip, off-chip termination was used. This disclosure proposes an on-chip termination scheme that is switchable, programmable, and variable.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

On-Chip Programmable Termination Scheme

      Communication between chips sometimes requires parallel
termination.  Before the existence of a resistance layer, on-chip,
off-chip termination was used.  This disclosure proposes an on-chip
termination scheme that is switchable, programmable, and variable.

      Fig. 1 shows a termination scheme in a transmission line
environment.  A termination is usually placed at the far end of the
transmission line.  Basically, termination consists of a tristate
inverter in series with an on-chip resistor.  There are many such
tristate inverter-resistor pairs in parallel, as shown in Fig. 2.

      The CMOS tristate inverter is shown in Fig. 3.  The inverter's
ENABLE pin is used to enable/tristate.  When ENABLE= "logic 1", both
QP2 and QN2 devices are off.  Then, output is the invert of input.
If input = "logic 1", QN1 is turned on, creating parallel termination
to ground.  If input = "logic 0", QP1 is turned on, creating parallel
termination to Vdd.  When ENABLE= "logic 0", both QP2 and QN2 devices
are on.  QP2, which is on, will pull node 1 (in Fig. 3) to Vdd,
turning off big device QP1.  Similarly QN2, which is on, will pull
node 2 to ground, turning off big device QN1.  With both QP1 and QN1
off, output OUT is floated; the inverter is tristated.  The Truth
Table summarizes the inverter's logic function.

   Truth Table
      IN         EN       OUT
      0          0       High Impedance
      0          1       0
      1          0       High Impedance
     ...