Browse Prior Art Database

Combined Status Poll and Completion Barrier

IP.com Disclosure Number: IPCOM000114958D
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Arndt, RL: AUTHOR [+2]

Abstract

The general structure of a computer system is shown in the Figure. In such a system, Programmed Input and Output (PIO) operations from the device driver may be queued in various locations in the system. In order for the device driver to assure that an operation has completed and completed properly, the device driver must generally perform a two step operation. First, it must assure that the operation is complete and second, it must get some kind of indication that the operation completed without error.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 62% of the total text.

Combined Status Poll and Completion Barrier

      The general structure of a computer system is shown in the
Figure.  In such a system, Programmed Input and Output (PIO)
operations from the device driver may be queued in various locations
in the system.  In order for the device driver to assure that an
operation has completed and completed properly, the device driver
must generally perform a two step operation.  First, it must assure
that the operation is complete and second, it must get some kind of
indication that the operation completed without error.

      Various I/O subsystems have taken various approaches to this
problem.  For example, some systems (especially Mult-Processor
systems) have some sort of synchronizing (SYNC) instruction.  This
SYNC instruction, when issued, assures that all operations which all
processors have outstanding in the system, are complete.  This
operation is then used to assure the PIO from the device driver has
been accepted by the device before a status register is read from the
device to check for successful completion.  The problem with this
approach is that it is very expensive from a performance standpoint,
since it forces all processors to wait for all operations to complete
before proceeding.

Fortunately, the Bus Unit Controller can reduce the SYNC overhead.
It contains all the information needed for signaling completion and
success.  We do this with an error status register in the Bus Unit
Controller.  The register...