Browse Prior Art Database

Data Transfer Mechanism for Personal Computer Memory Card International Association Interface to Digital Signal Processor

IP.com Disclosure Number: IPCOM000114965D
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 167K

Publishing Venue

IBM

Related People

Cope, BG: AUTHOR [+4]

Abstract

A mechanism for attaching a Digital Signal Processor (DSP) to a Personal Computer Memory Card International Association (PCMCIA) interface is disclosed. Access to DSP memory by the Personal Computer is made more efficient to provide the required data throughput since the PCMCIA interface does not allow DMA transfers.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 38% of the total text.

Data Transfer Mechanism for Personal Computer Memory Card International
Association Interface to Digital Signal Processor

      A mechanism for attaching a Digital Signal Processor (DSP) to a
Personal Computer Memory Card International Association (PCMCIA)
interface is disclosed.  Access to DSP memory by the Personal
Computer is made more efficient to provide the required data
throughput since the PCMCIA interface does not allow DMA transfers.

      The PCMCIA bus is an emerging standard for connecting adapter
cards to PCs (especially portables and laptops).  This bus is similar
to the standard AT / ISA bus used in most PCs, with some significant
limitations.  One of the most notable limitations is the inability to
support Bus Master or DMA transfers of data between the adapter card
and system memory.

      To circumvent the lack of DMA and bus mastering in the PCMCIA
world, a design using common memory, the single interrupt request
line, and the WAIT signal has been implemented.  DSP tasks continue
to request DMA transfers the same way as in Bus Master systems,
setting up control blocks and placing requests on the DMA queue.  The
difference is that the Data Mover task called by the MWAVE operating
system is changed to move the data from the user task to another
buffer space in DSP memory instead of activating the DMA hardware.
Once the data has been moved, an interrupt may be generated to the PC
to alert the driver code that there is data in the interface buffer.
The interrupt may be selectively generated only when the interface
buffer is approaching full, so that task switching overhead is
minimized.

      This approach could work without hardware change, but PC system
processor access to DSP RAM is cumbersome, requiring I/O accesses for
each location.  The circuit in the Figure was implemented to map
normal memory transfers on the PCMCIA bus into the required register
access on the internal ISA bus interface to the DSP.  This allows the
application driver code to use block memory moves which are more
efficient than individual I/O read and write instructions.

      The base of this design is a functional macro with an ISA bus
interface.  The DSP local data store SRAM (static RAM) appears as a
common memory window to the system and can be accessed directly.
Normal access to the SRAM in the ISA bus design requires a sequence
of I/O register accesses, first to set the access mode to select data
RAM (as opposed to instruction RAM), then to set the desired address,
and finally to read or write data.  Hardware has been added to
automatically map a memory access on the PCMCIA bus into the required
sequence of I/O register reads / writes at the ISA bus interface.

Only data RAM access is supported using the memory mapped access, so
the selection of access mode is skipped, and the memory mapped access
overrides whatever state the mode select register is in.  Instruction
RAM access will continue to require the I/O re...