Browse Prior Art Database

Method for Software to Flush/Invalidate DMA Buffers

IP.com Disclosure Number: IPCOM000114969D
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Arimilli, LB: AUTHOR [+4]

Abstract

Disclosed is a method to allow software the ability to flush/invalidate the DMA buffers of an I/O controller which provides the graphics interface to the RS/6000* System I/O (SIO) bus. This method does not require the addition of a new instruction to the instruction set.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 54% of the total text.

Method for Software to Flush/Invalidate DMA Buffers

      Disclosed is a method to allow software the ability to
flush/invalidate the DMA buffers of an I/O controller which provides
the graphics interface to the RS/6000* System I/O (SIO) bus.  This
method does not require the addition of a new instruction to the
instruction set.

      The I/O controller has two 32-byte DMA buffers.  The maximum
transfer size on the graphics bus is 32 bytes and the minimum DMA
transfer size on the SIO bus is 64 bytes.  Therefore, to avoid a
read-modify-write operation for DMA writes initiated by an adapter on
the graphics bus, the I/O controller assembles two consecutive
32-byte DMA writes in its buffers and generates one 64-byte DMA write
to system memory over the SIO bus.  For DMA reads, 64 bytes are
fetched at a time on the SIO bus and a maximum of 32 bytes are
requested at a time over the graphics bus.  If a DMA read to the next
consecutive 32 bytes is requested, the I/O controller can get this
data from its buffers instead of requesting it from system memory
over the SIO bus.

      There can be coherence problems between the data in the I/O
controller DMA buffers and the corresponding data in system memory.
For DMA writes, if a 32-byte DMA write on the graphics bus is not
followed by another DMA write or is followed by another DMA write at
a much later time, the data in the buffers can become stagnant or out
of date with corresponding data in system memory since the I...