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IEEE P1394 Link Level Virtual First In/First Outs for Command Block and Status Block Reception and Signalling

IP.com Disclosure Number: IPCOM000114992D
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 190K

Publishing Venue

IBM

Related People

Hoch, G: AUTHOR [+6]

Abstract

Disclosed is a mechanism which solves the problem of efficiently creating and managing areas in system memory to receive IEEE P1394 packets which contain command information or status information, and also a mechanism to signal a microproceesor upon said reception.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 32% of the total text.

IEEE P1394 Link Level Virtual First In/First Outs for Command Block
and Status Block Reception and Signalling

      Disclosed is a mechanism which solves the problem of
efficiently creating and managing areas in system memory to receive
IEEE P1394 packets which contain command information or status
information, and also a mechanism to signal a microproceesor upon
said reception.

      This invention relates to the IEEE 1394 High Performance Serial
Bus Standard, IEEE 1394/Draft 6.6v0, and to the ANSI Working Draft
X3T9.2-992D, SCSI-3 Serial Bus Protocol (hereafter simply referred to
as SBP).

      SCSI-3 Serial Bus Protocol (SBP) describes a command and status
delivery protocol for controlling the operation of serial SCSI
devices attached to an IEEE 1394 High Performance Serial Bus.  This
protocol integrates the Parallel SCSI Command Descriptor Block (CDB)
within the Serial SCSI Command Data Structure (CDS).

      One important difference between Parallel SCSI and Serial SCSI
(as defined by SBP) is the redistribution of the system DMA context
handling from the initiator (as in Parallel SCSI) out to the target
devices (for SBP Serial SCSI).  That is, the target device is given
the role of DMA context maintenance.  Of course SBP can only take
advantage of this because of the IEEE 1394 serial bus addressing
architecture.

      In general, DMA context maintenance means that the target
devices get CDS blocks from initiators that not only contain imbedded
CDBs, but also contain initiator system addresses of where to get
data and other CDSs and where to send data and status.  SBP targets
move data in and out of initiator memory space using IEEE 1394 Read
Request and Write Request packets that have initiator memory
addresses as part of the destination address for these packets.  This
is a nice feature for SBP Serial SCSI initiator hardware because it
provides what is viewed as a design simplification.  That is, the
simplification of the initiator to being just a IEEE 1394 packet
router once initialization is complete.  However, it also raises the
concern of how this packet router handles the reception of certain
packet types, and how the packet router can efficiently signal
(interrupt) a controlling microprocessor.

      This disclosure describes a means by which IEEE P1394 BLOCK
WRITE REQUEST or QUAD WRITE REQUEST packets which contain command or
status information are received from the IEEE P1394 bus into a link
level controller (LINK) chip main FIFO, after passing through a P1394
Physical level controller (PHY) chip, and then, automatically
deposited into pre-established virtual FIFOs in system memory.  Also,
described is the means by which signalling of interrupts will occur
to a host micrprocessor in relation to the above described system
memory virtual FIFOs.  A block diagram of the pack dataflow from PHY
chip to LINK chip is shown in Fig. 1

      The LINK chip contains 3 major functional blocks.  The...