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Address Mapping of Industry Standard Architecture Masters in the PowerPC Reference Platform

IP.com Disclosure Number: IPCOM000115010D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Curry, SE: AUTHOR [+6]

Abstract

Disclosed is a method which enables Industry Standard Architecture (ISA) master devices to access main memory on a PowerPC* Reference Platform system. This is accomplished by special logic that inhibits the inversion of the high-order address bit that normally occurs when PCI accesses memory.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 76% of the total text.

Address Mapping of Industry Standard Architecture Masters in the
PowerPC Reference Platform

      Disclosed is a method which enables Industry Standard
Architecture (ISA) master devices to access main memory on a PowerPC*
Reference Platform system.  This is accomplished by special logic
that inhibits the inversion of the high-order address bit that
normally occurs when PCI accesses memory.

      The architecture of the PowerPC Reference Platform requires PCI
devices to address main memory at 2 GB to 4 GB.  The PCI-to-CPU
bridge inverts PCIAD31 (the high-order address) during the address
phase to produce system memory addresses from 0 to 2 GB.

      Since by definition ISA masters reside on a 24-bit ISA bus,
their addressable memory range is 0 - 16 MB.  When this 24-bit
address is translated to a 32-bit address by a bridge device, the
address bits above 24 are undefined and usually zeroed by the bridge.
As a result, the ISA masters cannot directly address system memory
because the high-order address bit is inverted, producing addresses
from 2 GB to 4 GB which are out of the range of the system memory.

      To solve this problem, logic must provide a method to translate
the ISA address range to the range of system memory.  This is
accomplished by a PCI bridge and memory controller chip set, which is
comprised of a buffer chip and a control chip.

      In order to support ISA master accesses to system memory, the
control chip monitors the ISA maste...