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Browse Prior Art Database

Video Electronics Standards Association Display Data Channel-1 Capability on XGA-2 Sub-Systems

IP.com Disclosure Number: IPCOM000115013D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Harley, M: AUTHOR [+2]

Abstract

The Video Electronics Standards Association (VESA) have proposed the use of a Display Data Channel (DDC) in order that monitors and their attached systems might communicate [Ref VESA BIOS Extensions/Display Data Channel (VBE/DDC) Proposal v1.0p Rev 22p, 10 June 1994]. The minimum implementation (DDC-1) allows a monitor to "tell" the attached system information about its function etc. The system can then exploit the display to their mutually greatest advantage without direct user intervention (ie "Plug & Play"). The following describes a method of obtaining DDC-1 information from a display on any system which uses an XGA-2 graphics sub-system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 93% of the total text.

Video Electronics Standards Association Display Data Channel-1 Capability
on XGA-2 Sub-Systems

      The Video Electronics Standards Association (VESA) have
proposed the use of a Display Data Channel (DDC) in order that
monitors and their attached systems might communicate [Ref VESA BIOS
Extensions/Display Data Channel (VBE/DDC) Proposal v1.0p Rev 22p, 10
June 1994].  The minimum implementation (DDC-1) allows a monitor to
"tell" the attached system information about its function etc.  The
system can then exploit the display to their mutually greatest
advantage without direct user intervention (ie "Plug & Play").  The
following describes a method of obtaining DDC-1 information from a
display on any system which uses an XGA-2 graphics sub-system.

      In summary, DDC-1 capable displays serially transmit a 128-byte
message continuously to the attached graphics sub-system.  The data
is transmitted via a pin traditionally used for one of the Monitor ID
bits.  The data is clocked using the Vertical Synchronization (VSync)
signal.

      A very simple software routine can be executed to toggle the
VSync line (via the XGA Display Mode register on an XGA-2 Subsystem),
wait for the data to become valid and reading the data bit (via the
XGA Monitor ID register on an XGA-2 Subsystem).  This routine can be
repeated until all 128 bytes of the message have been read in.  Once
stored the message is scanned for the pre-defined header to identify
a start position.  The...