Browse Prior Art Database

Dynamic Relative Bus Operating Frequency Determination

IP.com Disclosure Number: IPCOM000115017D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 71K

Publishing Venue

IBM

Related People

Bui, HQ: AUTHOR [+6]

Abstract

Disclosed is a means to determine the relative operating frequency of the processor bus and the PCI bus in a PowerPC* system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 71% of the total text.

Dynamic Relative Bus Operating Frequency Determination

      Disclosed is a means to determine the relative operating
frequency of the processor bus and the PCI bus in a PowerPC* system.

      PCI-based systems consist of at least two independent
synchronous buses: the processor bus and the PCI bus.  These buses
may have independent operating frequencies.  In order to synchronize
events between the two buses, it is necessary for bridge hardware to
know (or determine) the relative bus operating frequency.

      Desktop PowerPC systems determine this frequency by sampling
the PCI bus clock at the processor bus clock frequency, then delaying
the result by a single processor clock cycle and comparing it
"exclusive or" (XOR) to the sampled value.

      The result of the comparison, which is placed in a register
each processor clock cycle, indicates the relative bus operating
frequency with a logical 1 indicating 2:1 clocking and a logical 0
indicating 1:1 clocking.

      The implementation is depicted in Fig.1 where CLK1 represents
the PCI bus clock and CLK2 represents the processor bus clock.  The
PCI bus clock functions as a DATA input which is sampled at a
frequency
equivalent to that of the processor bus clock.  Effectively, the PCI
bus
clock is sampled, delayed, and compared to itself to determine if the
operating frequency of the processor clock is the same (1:1) or twice
(2:1) that of the PCI clock operating frequency.

      Fig. 2 and Fig...