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Mechanism to Connect a Non-Accurate 64 KPBS Data Interface on a Time Division Multiplex Link

IP.com Disclosure Number: IPCOM000115034D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Calvignac, J: AUTHOR

Abstract

In the publication (*), a Time Division Multiplex link structure is described which allows to accommodate a plurality of users, for example 32 operating at any speed up to 64 kbps. Each user has an offering of two slots on the link, i.e., one 8-bit data slot and one 8-bit control slot. For logical user connections, the 64 kbps user data slot is synchronous with the Time Division Multiplex clocking. For a 64 kps physical attachment, the clocking is derived from an oscillator in the modem or the terminal equipment and the clocking accuracy is typically 10-4 or 10-5. This means that for a nominal speed of 64 kpbs, the link offering will correspond to transfers of up to 9 bits.

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Mechanism to Connect a Non-Accurate 64 KPBS Data Interface on a Time
Division Multiplex Link

      In the publication (*), a Time Division Multiplex link
structure is described which allows to accommodate a plurality of
users, for example 32 operating at any speed up to 64 kbps.  Each
user has an offering of two slots on the link, i.e., one 8-bit data
slot and one 8-bit control slot.  For logical user connections, the
64 kbps user data slot is synchronous with the Time Division
Multiplex clocking.  For a 64 kps physical attachment, the clocking
is derived from an oscillator in the modem or the terminal equipment
and the clocking accuracy is typically 10-4 or 10-5.  This means that
for a nominal speed of 64 kpbs, the link offering will correspond to
transfers of up to 9 bits.  The mechanism described in this article,
allows an interface to perform 9-bit transfers in order to support
data transfers at up to 64 kbps with a not accurate line clock.

      For transmit operations (Fig. 1A), 10 bits can be exchanged at
each link offering opportunity, including up to 9 valid data bits X
and a delimiter (V).  The spare bit of the transmit control slot is
used as a 10th bit of the delimiter which is in fact an additional
global validation bit called G.  It indicates whether a 9 bit data
transfer is taking place (G'=1) or not (G'=0).  When G'=1, G-bit is
used to carry the 9th data bit.

      In case of speeds near 64 kbps with a non accurate line clock,
data transfers are 9-bit length anytime a transmit request is
received in the receive control slot.  From time to time no transmit
request is received and an empty data slot will be...