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Testable Digital Delay Line

IP.com Disclosure Number: IPCOM000115037D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

LeBlanc, J: AUTHOR [+3]

Abstract

A design for a testable digital delay line is shown. This allows for a selective delay of a signal, usually a clock. It fixes the shortcomings of some designs by including an enhanced ability to detect circuit faults.

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Testable Digital Delay Line

      A design for a testable digital delay line is shown.  This
allows for a selective delay of a signal, usually a clock.  It fixes
the shortcomings of some designs by including an enhanced ability to
detect circuit faults.

      A Digital Delay Line has multiple delay taps.  The outputs feed
one or more multiplexers, in order to select a delayed version of the
input.  In an implementation with a normal multiplexer, there are
redundancies in the logic which make it impossible to sense stuck-at
faults in the selection logic.  Previous versions of solutions
involve logic which adds excess logic or delay.

      A normal multiplexer is extended through the use of discrete
gates and parity logic.  Selection logic attached to it then allows
selection of any port, but failures of the select logic are caught
and not propagated.

      The additional logic required is the addition of a parity
generator, which is an exclusive-or of the other inputs, and slightly
more complex selection logic.

      By limiting the path from the delay ports to the AND through a
two input OR gate, the delay (and therefore delay variation) is
minimized.  By adding the parity bit to the multiplexer, there is
redundancy added to the logic, where a single failure in the select
logic degates all clocks instead of selecting the wrong delay value
clock.  LSSD can selectively enable any particular delay path through
scanning in the required select, an...