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Browse Prior Art Database

Slew Rate Controlled Circuit

IP.com Disclosure Number: IPCOM000115046D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 75K

Publishing Venue

IBM

Related People

Cao, A: AUTHOR [+3]

Abstract

For high speed applications where high performance circuits are used, a problem circuit and packaging noise becomes dominant. When noise becomes severe, circuit degradation along with performance suffers, and one critical noise is in off-chip slew rate performance.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Slew Rate Controlled Circuit

      For high speed applications where high performance circuits are
used, a problem circuit and packaging noise becomes dominant.  When
noise becomes severe, circuit degradation along with performance
suffers, and one critical noise is in off-chip slew rate performance.

      The driver design noise can be controlled with the switching
rise and fall times.  The rise/fall times are among the slew rate
parameters of driver design.  Performance slew rate determines the
amount of circuit noise created by cross-talk, delta-I noise.

      As shown in Fig. 1, the block diagram consists of an output
stage of driver fall circuit signals C1, C2, ...  CN.  The pre-driver
stage is at the input of the part of data flow; all functional data
must come from the pre-drive stage to the driver circuit.  Control
circuits control the flow of data into the output.

      Fig. 2 shows the proposed circuit scheme to control the slew
rate of the output.  The circuit is a CMOS driver consisting of an
output stage of a P-device (P8) and an N-device (N8).  Typically,
these devices are designed with low impedance in mind to source/sink
a current.  In terms of physical design, these devices are made large
and consequently their input capacitances are high.  Control circuits
are made of pass devices N2, N6, ... (N-devices) and P2, P3, ...,
P5, P6, ... (P-devices) and each of their g by signals C1, C2, ...,
CN.  Data flows from the inverter buffer circuit consisting of an N1
(N-device).

      When pass gate devices are 'on' by combination of control
signals C1 or C2 or CN, the data path to the output stage is shown in
Fig. 3 as an equivalent circuit.  The Basic RC delay circuit can be
controlled by a number of control signals.  The slew rate (dv/dt) of
the gate voltage of the driver output stage can be defined b...