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Low Voltage Complementary Metal-Oxide Semiconductor Charge Pump Without Common Mode Feedback

IP.com Disclosure Number: IPCOM000115048D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Schulte, DJ: AUTHOR [+2]

Abstract

A differential low voltage Complementary Metal-Oxide Semiconductor (CMOS) charge pump circuit topology that doesn't require a common mode feedback loop is disclosed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Low Voltage Complementary Metal-Oxide Semiconductor Charge Pump Without
Common Mode Feedback

      A differential low voltage Complementary Metal-Oxide
Semiconductor (CMOS) charge pump circuit topology that doesn't
require a common mode feedback loop is disclosed.

      A typical differential charge pump requires a common mode
feedback loop to hold the differential value of the output voltage
when neither the increment or decrement signal is active (hold mode).
When the charge pump is in the hold state, the common mode loop
assures that the differential charge pump output voltage does not
change or drift with over.  The common mode feedback loop must have a
gain of one so that it does not effect the charge pump differential
output voltage and must be stable under all conditions to assure the
loop doesn't oscillate.  These requirements coupled with low power
supply voltages make designing the common mode feedback difficult.
Thus, a motivation exist for a charge pump circuit scheme that
doesn't require a common mode feedback loop.

      By forcing the charge pump into a high impedance state during
the "hold mode", the differential output voltage is preserved and the
common mode feedback loop can be avoided.  This is accomplished with
the circuit shown in the Figure.  In this circuit, the differential
inputs INC and INCN are the increment (up, increase) control signals
and DEC, DECN are the decrement (down, decrease) control signals.
The input VNBIAS biases NFET's T6 and T7 as current sources
condu...