Browse Prior Art Database

High Performance, Low Input Capacitance, Optimal BiCMOS Driver for Static Decoder

IP.com Disclosure Number: IPCOM000115055D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Aipperspach, AG: AUTHOR [+3]

Abstract

Disclosed is a decoder that provides a high performance design but minimizes the loading on the address inputs making it simpler to design symmetrical setup/hold.

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High Performance, Low Input Capacitance, Optimal BiCMOS Driver for
Static Decoder

      Disclosed is a decoder that provides a high performance design
but minimizes the loading on the address inputs making it simpler to
design symmetrical setup/hold.

      The circuit operates in the following manner.  When the decoder
is selected, the A1/A2 inputs will both be high.  When the clock
signal goes high (A0), the NPN T3 will be activated and quickly pull
the output node 10 low.  When the clock goes low, the transistor T4
activates and restores the 10 node high.  In the case where the the
decoder is not selected, the clock will deactivate the pullup
transistor T4, but the small latch back inverters will retain the
state of the output.

      In addition to being a high performance solution to the problem
described above, the removal of the complementary P-type network also
reduces the physical area of the circuits and makes them easier to
lay out on the pitch of the storage cells (Figure).