Browse Prior Art Database

Orthogonal Test Pattern Generator

IP.com Disclosure Number: IPCOM000115076D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 85K

Publishing Venue

IBM

Related People

Jaber, T: AUTHOR [+3]

Abstract

Disclosed is a design that generates orthogonal test patterns to test orthogonal logic.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Orthogonal Test Pattern Generator

      Disclosed is a design that generates orthogonal test patterns
to test orthogonal logic.

      An orthogonal circuit is a circuit that only operates correctly
when one and only one input is high.  If more than one input is high,
this orthogonal circuit under test could either produce an
indeterminate state or result in a functional failure.  In system
operation, it is guaranteed that only one of the inputs can be high.

      This functional behavior creates a serious problem in testing
when weighted random patterns (WRPs) or pseudorandom patterns are
applied.  Previous approach is to use priority logic (e.g., RIOS1 and
RIOS2) to guarantee that only one of the inputs can be high.  It
works; however, the additional delay introduced by the priority logic
slows down system performance.  It is not acceptable for the 630
chip.

      An alternative solution is proposed.  This proposal uses a
pseudo-PRPG to generate a desired pattern sequence and eliminates the
need for additional logic in the functional paths.  The operation of
this proposed design can be summarized as follows:
  Definitions:
  PRPG2: A pseudo-PRPG generator that is depicted in Fig. 1.  In scan
   mode, the circuit is initialized to 1,0,0,.....0.  The length of
this
   scan string is 31 bits.  In WRP/COP mode, S.T.  input is set to
'1'
   and the content of SRLs shifts with the scan clocks.  The result
of
   this operation produces 'walking-one patterns'.
  Orthogonal Logic: An orthogonal logic can only allow one of its
   inputs to be '1', independent of...