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Adaptive Interface Circuit which Allows Basic Transferts between a Slave Device and Different Hosts

IP.com Disclosure Number: IPCOM000115079D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 166K

Publishing Venue

IBM

Related People

Godefroy, C: AUTHOR [+3]

Abstract

Most circuits are designed for a target BUS or host system. This limits the use of these circuits in a different system because of the need of glue logic to adapt the circuit protocol to the system protocol. The glue logic can be so complex that an ASIC is dedicated for that purpose. The principal object of this interface is to show that with only a limited number of gates integrated in the device circuit, it is possible to connect the device to several different buses, especially an asynchronous BUS like the ISA bus or a synchronous multiplexed bus like the PCI. It allows basic transferts; some features of the standard buses are not supported. Of course, not only some logic gates are dedicated to this circuit, but also some additionnal inputs and outputs as described below.

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This is the abbreviated version, containing approximately 49% of the total text.

Adaptive Interface Circuit which Allows Basic Transferts between
a Slave Device and Different Hosts

      Most circuits are designed for a target BUS or host system.
This limits the use of these circuits in a different system because
of the need of glue logic to adapt the circuit protocol to the system
protocol.  The glue logic can be so complex that an ASIC is dedicated
for that purpose.  The principal object of this interface is to show
that with only a limited number of gates integrated in the device
circuit, it is possible to connect the device to several different
buses, especially an asynchronous BUS like the ISA bus or a
synchronous
multiplexed bus like the PCI.  It allows basic transferts; some
features
of the standard buses are not supported.  Of course, not only some
logic
gates are dedicated to this circuit, but also some additionnal inputs
and
outputs as described below.

      Now referring to Fig. 1, BOX 10 comprised of blocks 11 to 15
illustrates the functions of the interface circuit and the
input/output signals:
  Input:
  1.  CS_ : chip select, can be used as strobe on PC BUS (ISA,
PCMCIA,
       MC) when AS_ and DS_ are tied to "0".
  2.  AS_ : address strobe.  For the PC BUS: the IOW or IOR must be
       connected to this input.
  3.  The PCI FRAME_ signal is connected to this input.  For the
power
       PC 601, the TS (transfert start) signal is connected to this
       input.
  4.  DS_ : data strobe.  This signal controls the state machine.
When
       this signal is hold active (for example for an asynchronous
       protocol like the ISA BUS), the output is maintained on the
BUS
       until this signal is released.  For the PC BUS, the IOW or IOR
       must be connected to the input.  For the PCI BUS, IRDY_ must
be
       connected to this input if WAIT STATE are generated by the
       master.  If no WAIT STATE are generated by the master, the DS_
       can be tied to "0" because the FRAME signal then controls the
       state machine.  For the power PC 601, the DBB bar (data bus
busy)
       must be connected to thin input.
  5.  SYNC must be hold to "1" for the PCI synchronous protocol.
  6.  SYS_CLK . A square clock must be connected to this input.
  7.  STANDBY when set to "1", the clock is gated.  The chip is in
       standby mode.
  Output:
  1.  WAIT_ is used by a PC PIO BUS.
  2.  ACK_  is the address acknowledge signal for the POWER PC 601
BUS
       and the strobe acknowledge for the PCMCIA BUS.
  3.  RDY_ is the ready signal for the MOTOROLA 68xxx or the POWER PC
       601 or the PCI BUS.
  4.  DSEL_ : device select is for the PCI BUS.
  5.  IRQ_ : interrupt request, can be used by all BUS.
  Blocks 11, 12 and 13 are shown in details in Fig. 2 which is
comprised of Figs. 2A and 2B.

      Now referring to Fig.2, box 13 generates the single shot pulse
in...