Browse Prior Art Database

Voltage Controlled Oscillator Control Loop Scheme for Low Jitter Applications

IP.com Disclosure Number: IPCOM000115083D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 77K

Publishing Venue

IBM

Related People

Schulte, DJ: AUTHOR [+2]

Abstract

A Voltage Controlled Oscillator (VCO) control loop scheme which uses a secondary tracking VCO and digital control loop to compensate for process, power supply and temperature variations is disclosed. This compensation scheme allows the "real" VCO in a phase lock loop (PLL) system to be designed with less linear range and lower gain which results in a simpler VCO design and less output jitter.

This text was extracted from an ASCII text file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Voltage Controlled Oscillator Control

Loop

Scheme for Low Jitter
Applications

      A Voltage Controlled Oscillator (VCO) control loop scheme which
uses a secondary tracking VCO and digital control loop to compensate
for process, power supply and temperature variations is disclosed.
This compensation scheme allows the "real" VCO in a phase lock loop
(PLL) system to be designed with less linear range and lower gain
which results in a simpler VCO design and less output jitter.

      In order to lower the gain of the main VCO/PLL and thereby
reduce the sensitivity to jitter, a tracking VCO and digital control
loop were added as shown below the dashed line in the figure.
Physically, the tracking or dummy VCO is placed in close proximity to
the real VCO so it tracks the performance of the real VCO shown above
the dashed line in the figure.

      The dummy VCO has a digital control loop comprised of a
frequency counter, center frequency register, digital comparator,
up/down counter and a digital-to-analog converter (DAC).  A
divide-by-X version of the crystal oscillator is used to gate the
frequency counter for a specified period (X * Tc/2) during which the
counter counts the number of cycles that the divided-by-N output of
the dummy oscillator toggles in this time.  This cycle count
(frequency) is then compared to the desired value stored in the
center frequency register.  If the count from the dummy oscillator is
to low, the comparator asserts the UP signal and increments the count
from the Up/Down counter.  This causes the output of the DAC to
increase which in turn increases the output frequency of the dummy
VCO.  A small state machine (not shown) is needed to reset the
counter and hold the output of the DAC in this state until the next
frequency comparison is done.  This frequency com...