Browse Prior Art Database

Look-aside Store-in Cache Controller for Personal Computers

IP.com Disclosure Number: IPCOM000115098D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 134K

Publishing Venue

IBM

Related People

Haig, RB: AUTHOR [+4]

Abstract

Disclosed is a architectural implementation to provide a Look-Aside Store-In Cache Controller (LASICC) for Personal Computers (PCs) which functions as a complete secondary cache subsystem. The controller is designed to increase the overall performance of a PC system and can be either an integral part of a system, or can be pluggable by the user.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 41% of the total text.

Look-aside Store-in Cache Controller for Personal Computers

      Disclosed is a architectural implementation to provide a
Look-Aside Store-In Cache Controller (LASICC) for Personal Computers
(PCs) which functions as a complete secondary cache subsystem.  The
controller is designed to increase the overall performance of a PC
system and can be either an integral part of a system, or can be
pluggable by the user.

      The LASICC is designed to be a complete secondary cache
subsystem for use with Intel i486* type of Central Processing Units
(CPUs), or CPUs that have similar bus interfaces including those
which can perform memory write bursts.  A memory write burst
operation is normally performed by store-in CPU driving L1 cache line
evictions onto the bus with zero wait states.

      The cache offers the flexibility of write-back and
write-through operations and is supported on a line by line basis in
the cache.  The cache supports CPUs that have both write-through and
write-back first level caches.  Each line in the cache can be
individually marked for either write-back, or write-through,
operations.  It also supplies data to the CPU in zero wait states for
cache read hit bus cycles and to accept data from the CPU in zero
wait states for write cycles which hit a cache line.

      The LASICC obtains the CPU local bus so as to write-back dirty
lines.  The cache will detect when a cacheable read miss occurs and
that there already is a dirty line at that cache index.  In this
case, the system cache will immediately, and before the first
transfer of the read miss line fill occur, drive the backoff to the
processor to gain control of the CPU local bus.  Then the system
cache will drive out CPU like bus cycles to perform the write-back of
the dirty line in four double word transfer.

      The Figure shows a block diagram of the use of LASICC in a
system.  CPU 10 contains first level CPU cache 11 and is connected to
memory controller 13 and memory units 15 through data bus 12.  LASICC
14 connects to data bus 12 through interconnect signal protocol 17.
This protocol defines the LASICC operation with CPU 10 and memory
controller 13 using control signals 16.
  The LASICC provides ten basic functions as follows:
  1.  RESET - The control logic is reset when the reset input is
       sampled high.  Any cycle that the cache is currently
processing
       will be aborted immediately if reset is sampled active.  Reset
       will invalidate the entire cache contents when it is asserted.
       All cache valid bits will be cleared when reset is asserted.
All
       other inputs to the cache are ignored when the reset input is
       asserted.
  2.  FLUSH - The cache will detect the high to low transition and
set
       a flush pending state.  The next CPU Input/Output (I/O) cycle,
       with the flush pending state set, will be backed off by the
       cache.  In...