Browse Prior Art Database

Single Clock Master Slave Latch

IP.com Disclosure Number: IPCOM000115110D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 100K

Publishing Venue

IBM

Related People

Dutta, S: AUTHOR [+2]

Abstract

High performance microprocessor applications require minimum delay skew for latch clocking so that no cycle time is wasted due to unusable parts of the clock cycle. This disclosure provides four master-slave latch designs that will operate with a single distributed clock so as to achieve minimum effective skew for best possible microprocessor system performance.

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Single Clock Master Slave Latch

      High performance microprocessor applications require minimum
delay skew for latch clocking so that no cycle time is wasted due to
unusable parts of the clock cycle.  This disclosure provides four
master-slave latch designs that will operate with a single
distributed clock so as to achieve minimum effective skew for best
possible microprocessor system performance.

      This disclosure claims four schematic latch circuit designs as
novel (pending a search) that allows the use of a single clock phase
or single clock signal to control the latch operation in a
master-slave (L1-L2) fashion.  The ability to use a single clock
results in minimum clock skew to the system design.  This is becoming
much more important as technology advances allow for cycle time
reduction but clock skew has not been reduced proportionately.

Figs. 1 through 4 show four schematics for four masterslave latches.

      The common element for all four schematics is that they operate
from a single clock input labeled "C".  Note that N-type transistors
are labeled "N" and P-type transistors are labeled "P".  The rise of
the clock signal turns on or opens up the first N-type transistor
allowing the input data to pass thru and reach the input to the
second inverter.  The input data is captured at this point when the
clock input signal falls to ground (appx) and the N-type transistor
turns off.

      The mechanism for capturing the input data is different for the
four schematics and works as follows:
  1) Static capture.... Fig. 1 schematic feeds back the output of
      the second inverter thru a third inververter to a P-type
transistor
      which is then connected back to the input of the second
inverter.
      The P-type transistor is on when the clock is at a down level
and
      the input data is statically captured.
  2) Dynamic capture... is used in the schematic shown in figure
      2 by storing the data input signal on the inherent capacitance
      of the ciruit C1 as shown in the schematic.  This type of
storage
      or capture is used in the schematics of both Fig. 2 and Fig. 4.
  3) Semi-static capture is found in Fig. 3 where if the data
      input signal at the input to the second inverter is a "1" or
      pos...