Browse Prior Art Database

Splitting of Bus Operation

IP.com Disclosure Number: IPCOM000115112D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 87K

Publishing Venue

IBM

Related People

Hilgendorf, R: AUTHOR

Abstract

A bus coupler is described for coupling two buses of different widths together. Fig. 1 shows the structure of the system with two bus couplers BK1 and BK2 connecting a plurality of bus units BU to a memory MEM and a processor PROC. The I-Bus connecting the bus units

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This is the abbreviated version, containing approximately 52% of the total text.

Splitting of Bus Operation

      A bus coupler is described for coupling two buses of different
widths together.  Fig. 1 shows the structure of the system with two
bus couplers BK1 and BK2 connecting a plurality of bus units BU to a
memory MEM and a processor PROC.  The I-Bus connecting the bus units

BU has the capability of 128 byte blocktransfers and the S-Bus
connecting the memory MEM and processor PROC to the bus coupler BK1
has only 64 bytes transferunits.  Using the bus coupler described it
is possible to carry out two read or two write operations on the
S-Bus if the two operations use 64 byte data blocks whose address are
an uneven multiple of 64 bytes from each other.  An example of such
an operation is a 128 byte read operation.

      The 128 byte read operation is split by the bus coupler into
two 64 byte read operations which, apart from the data addresses, are
identical to each other.  The read operation is carried out by
generating two requests (REQ-1 and REQ-2 signals), confirming the
validity of the command (CMD_VALID signal), transmitting the data and
finally transmitting an operation end signal.

      Fig. 2 shows an implementation of the bus coupler BK1.  From
the V-Bus controller, a request signal REQ is transmitted to the
flip-flop 1 concurrently with the loading of the command register
CMDREG and address register ADDRESS.  The output of the flip-flop 1
is transferred either to the AND-OR gates 5 or AND-OR gates 6 and
hence to the S-Bus controller 7.  Which request is activated depends
on addressbit 6.

      If the decoder 3 has detected a Read 128 byte command, then the
multiplexer 4 is set such that the S-Bus controller 7 receives a Read
64 byte command rather than the original comman...