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Method/Apparatus for Verifying Error-Checking-and-Correcting Hardwared Logic of a Memory Subsystem

IP.com Disclosure Number: IPCOM000115114D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 160K

Publishing Venue

IBM

Related People

Hinojosa, J: AUTHOR [+2]

Abstract

Disclosed is the method/apparatus which provides an easy and direct way to verify the proper functioning of the Error-Checking-and-Correcting (ECC) protection logic of the ECC memory subsystem in a computer system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 36% of the total text.

Method/Apparatus for Verifying Error-Checking-and-Correcting Hardwared
Logic of a Memory Subsystem

      Disclosed is the method/apparatus which provides an easy and
direct way to verify the proper functioning of the
Error-Checking-and-Correcting (ECC) protection logic of the ECC
memory subsystem in a computer system.

      Advanced computer systems normally implement their memory
subsystems with an ECC hardware mechanism for data integrity
protection of the memory storage array.  An ECC-doubleword (8-byte)
memory subsystem will need eight ECC check-bits per doubleword.
These check-bits are solely used by the ECC hardware logic for
protection purpose.  Specifically, these check-bits are inaccessible
to the system processors during normal operation.  However, the
effectiveness of the ECC protection also depends on having a good ECC
check-bit storage array.

      With no loss of generality, the method/apparatus will be
described using an ECC memory subsystem with ECC-doubleword
protection.  To allow the system processor direct access to the eight
ECC check-bits, i.e., the ECC-byte, by load/store machine
instructions,
this memory subsystem will have the following operating modes:

      A.  ECC-generation-off mode - This mode overrides other modes.
When this mode is active, the ECC logic will be completely disabled.
When a doubleword is written, a pre-selected byte within the
doubleword is forced to be written with data 0x00 (Hex).  The other
seven bytes of the doubleword are written as usual with their
supplied data values.  Moreover, the data value supplied by the write
access for the pre-selected byte is used to write into the ECC-byte
of the doubleword.  When a doubleword is read, the data value of the
pre-selected byte is provided by the ECC-byte.  The data values of
the other seven bytes are provided as usual from their memory storage
locations.  For the discussion, let's assume that the pre-selected
byte is named Byte0 of a doubleword.  Other bytes of a doubleword are
named Byte1, Byte2, ..., and Byte7.  Thus, the value of a doubleword
Dword is equal to
  Dword = (Byte0 << 56) + (Byte1 << 48) + ... + (Byte6 << 8) + Byte7
  where "<<" indicates the bitwise shift-left operation.

      B.  ECC-checking-off mode - When this mode is active, the ECC
generation logic is enabled.  A doubleword write access will be
carried
out as usual with supplied data value written into the doubleword's
memory location.  The ECC-byte is generated by the ECC logic and
stored
in the corresponding ECC-byte location of the doubleword.  A
doubleword
read access will reverse the process with data value coming from the
memory location of the doubleword.  The ECC-byte is also read by the
hardware and used for ECC checking-logic.  However, the result
of the checking does not affect the read access.  In short, data is
just
provided exactly as it is retrieved from the memory array.  No error
status is reported.

      C. E...